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浙江大学学报(工学版)
浙江大学学报(工学版)  2019, Vol. 53 Issue (4): 794-800    DOI: 10.3785/j.issn.1008-973X.2019.04.021
电子工程、电气工程     
新型VBO接口芯片静电放电防护器件
徐泽坤(),沈宏宇,胡涛,李响,董树荣*()
浙江大学 微电子学院ESD实验室，浙江 杭州 310027
New electrostatic discharge protection device for VBO high speed chip
Ze-kun XU(),Hong-yu SHEN,Tao HU,Xiang LI,Shu-rong DONG*()
School of Microelectronics ESD Laboratory, Zhejiang University, Hangzhou 310027, China
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摘要：

为了改进VBO接口电路静电放电（ESD）防护器件性能，提出2种新的ESD防护器件：栅二极管与面积效率二极管触发可控硅整流器（SCR）. 采用SMIC 40 nm CMOS工艺与SMIC 28 nm PS CMOS工艺制备传统二极管、栅二极管、面积效率SCR；通过半导体工艺及器件模拟工具（TCAD）进行仿真，分析电流密度；通过传输线脉冲测试（TLP）方法，测试不同结构ESD防护器件的Ⅰ-Ⅴ特性. 栅二极管的ESD鲁棒性为19.7 mA/μm，导通电阻为1.28 Ω，相较于传统二极管降低了38.8%. 面积效率二极管触发SCR触发电压为1.82 V，鲁棒性为48.1 mA/μm，相较于传统二极管提升了174.8%. 测试结果表明，栅二极管与ASCR和传统ESD器件相比，性能有极大的提升，适合用作VBO接口芯片的ESD防护.
关键词： 静电放电(ESD);  VBO;  可控硅整流器(SCR);  面积效率;  触发电压    
Abstract:

Two new electrostatic discharge (ESD) protection devices, gate diode and area-efficiency diode-trigger silicon controlled rectifier (SCR), were proposed in order to improve the performance of ESD protection devices on VBO interface circuit. Traditional diodes, gated diodes, and area-efficient SCR were fabricated based on SMIC 40 nm CMOS process and SMIC 28 nm PS CMOS process. The total current densities of those three structures were analyzed with the simulation of TCAD software. Ⅰ-Ⅴ characteristics of those ESD protection devices were measured by transmission line pulse (TLP) testing after tape-out. The gate diode's ESD robustness was 19.7 mA/μm, and on-resistance was 1.28 Ω with a 38.8% reduction compared to conventional diode. The trigger voltage of area-efficiency diode trigger SCR was 1.82 V and robustness of it was 48.1 mA/μm, which was a 174.8% improvement over conventional diode. The test results show that the performance of the gate diode and the ASCR is greatly improved compared to the conventional ESD device and is suitable to be the ESD device of VBO interface chip.
Key words: electrostatic discharge (ESD)    VBO    silicon controlled rectifier (SCR)    area efficiency    trigger voltage
收稿日期: 2018-05-06 出版日期: 2019-03-28
CLC:  TN 335  
通讯作者: 董树荣     E-mail: xzkis1@163.com;dongshurong@zju.edu.cn
作者简介: 徐泽坤(1996—)，男，硕士生，从事集成电路静电防护研究. orcid.org/0000-0001-6552-0689. E-mail: xzkis1@163.com
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引用本文:

徐泽坤,沈宏宇,胡涛,李响,董树荣. 新型VBO接口芯片静电放电防护器件[J]. 浙江大学学报(工学版), 2019, 53(4): 794-800.

Ze-kun XU,Hong-yu SHEN,Tao HU,Xiang LI,Shu-rong DONG. New electrostatic discharge protection device for VBO high speed chip. Journal of ZheJiang University (Engineering Science), 2019, 53(4): 794-800.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2019.04.021    或    http://www.zjujournals.com/eng/CN/Y2019/V53/I4/794

图 1  V-By-One接口的静电防护防护电路
图 2  VBO接口芯片失效分析
图 3  栅二极管与浅槽隔离二极管的横截面图
图 4  传统浅槽隔离二极管与栅二极管TLP曲线
图 5  栅二极管与浅槽隔离二极管电流密度仿真图
图 6  GFDiode和GSDiode以及GDDiode TLP曲线
图 7  3个二极管触发SCR横截面图
图 8  ASCR俯视图与横截面图
图 9  不同阶段ACR电流密度仿真
图 10  ASCR TLP测试曲线以及VF-TLP测试曲线和VF-TLP瞬态电压曲线
图 11  不同D1和D2参数下ASCR TLP测试曲线
文献 名称 尺寸/μm2 Vt/V Ton/ns Rou/（mA·μm?1）
文献[14] ILVTSCR 9×50 2.2 1.25 38.0
文献[14] DTSCR 12×50 2.5 NA 38.6
文献[15] DTSCR 8×60 2.86 NA 40.8
本文 ASCR 6.65×30 1.82 1.344 48.1
表 1  不同高速接口电路ESD防护方案性能对比
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