自动化技术、计算机技术 |
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新型电流型CMOS四值边沿触发器设计 |
杭国强1,应时彦2 |
(1.浙江大学 信息与通信工程研究所,浙江省综合信息网技术重点实验室,浙江 杭州 310027;
2.浙江工业大学 信息工程学院,浙江 杭州 310014) |
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Novel current-mode CMOS quaternary edge-triggered flip-flops |
HANG Guo-qiang1, YING Shi-yan2 |
(1. Institute of Information and Communication Engineering, Zhejiang Provincial Key Laboratory of Information Network Technology, Zhejiang University, Hangzhou 310027, China;
2. College of Information Engineering, Zhejiang University of Technology, Hangzhou 310014, China) |
[1] TANNO K, ISHIZUKA O. Survey of multiple-valued circuit technologies [C]∥ International Workshop on Post-Binary ULSI Systems. Boston: IEEE, 2002.
[2] CURRENT K W. Current-mode CMOS multiple-valued logic circuits [J]. IEEE Journal of Solid State Circuits, 1994, 29(2): 95-107.
[3] ISHIZUKA O, OHTA A, TANNNO K, et al. VLSI design of a quaternary multiplier with direct generation of partial products [C]∥ Proceedings of the International Symposium on Multiple-Valued Logic. Antigonish: IEEE, 1997: 169-174.
[4] IKE T, HANYU T, KAMEYAMA M. Fully source-coupled logic based multiple-valued VLSI [C]∥ Proceedings of the International Symposium on Multiple- Valued Logic. Los Alamitos: IEEE, 2002: 270-275.
[5] 杭国强,任洪波,吴训威. 基于控阈技术的四值电流型CMOS电路设计[J]. 半导体学报, 2002, 23(5): 523-528.
HANG Guo-qiang, REN Hong-bo, WU Xun-wei. Design of current-mode CMOS quaternary circuits based on threshold-controllable technique [J]. Chinese Journal of Semiconductors, 2002, 23(5): 523-528.
[6] 杭国强. 基于控阈技术的电流型CMOS全加器的通用设计方法[J]. 电子学报, 2004, 32(8): 1367-1369.
HANG Guo-qiang. Universal design method for current-mode CMOS adders based on threshold-controllable technique [J]. Acta Electronica Sinica, 2004, 32(8): 1367-1369.
[7] ABD-EL-BARR M, AL-MUTAWA A. A new improved cost-table-based technique for synthesis of 4-valued unary functions implemented using current-mode CMOS circuits [C]∥ Proceedings of the International Symposium on Multiple-Valued Logic. Warsaw: IEEE, 2001: 15-20.
[8] MOCHIZUKI A, HANYU T. Low-power multiple- valued current-mode logic using substrate bias control [J]. IEICE Transactions on Electronics, 2004, E87-C(4): 582-588.
[9] 杭国强,吴训威. 一种单锁存器CMOS 三值D型边沿触发器设计[J]. 电子学报,2002, 30(5): 760-762.
HANG Guo-qiang, WU Xun-wei. CMOS ternary D-type edge-triggered flip-flop using one latch [J]. Acta Electronica Sinica, 2002, 30(5): 760-762.
[10] KIM C, KANG S M. A low-swing clock double-edge triggered flip-flop [J]. IEEE Journal of Solid-State Circuits, 2002, 37(5): 648-652. |
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