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基于邻行链接访问的低功耗指令高速缓存 |
项晓燕,陈志坚,孟建熠,严晓浪 |
浙江大学 超大规模集成电路设计研究所,浙江 杭州 310027 |
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Low power instruction cache based on adjacent line linking access |
XIANG Xiao-yan, CHEN Zhi-jian, MENG Jian-yi, YAN Xiao-lang |
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China |
引用本文:
项晓燕,陈志坚,孟建熠,严晓浪. 基于邻行链接访问的低功耗指令高速缓存[J]. J4, 2013, 47(7): 1213-1217.
XIANG Xiao-yan, CHEN Zhi-jian, MENG Jian-yi, YAN Xiao-lang. Low power instruction cache based on adjacent line linking access. J4, 2013, 47(7): 1213-1217.
链接本文:
http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2013.07.012
或
http://www.zjujournals.com/eng/CN/Y2013/V47/I7/1213
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[1] GONZALEZ R, HOROWITZ M. Energy dissipation in general purpose microprocessors [J]. IEEE Journal of Solid-State Circuits, 1996, 31(9):1277-1284.
[2] 孟建熠,严晓浪,葛海通,等.基于指令回收的低功耗循环分支折合技术[J].浙江大学学报:工学版, 2010, 44(4): 632-638.
MENG Jian-yi, YAN Xiao-lang, GE Hai-tong, et al. Instruction recycling based low power branch folding [J]. Journal of Zhejiang University: Engineering Science, 2010,44(4):632-638.
[3] TSAI Y Y, CHEN C H. Energy-efficient trace reuse cache for embedded processors [J]. IEEE Transactions on Very Large Scale Integration Systems, 2011,19(9):1681-1694.
[4] HASEGAWA A, KAWASAKI I, YAMADA K, et al. SH3: high code density, low power [J]. IEEE Micro, 1995, 15(6): 11-19.
[5] INOUE K, ISHIHARA T, MURAKAMI K. Way-predicting set-associative cache for high performance and low energy consumption [C]∥ Proceedings of ISLPED. California: [s.n.], 1999: 273-275.
[6] XU C P, ZHANG G, HAO S Q. Fast way-prediction instruction cache for energy efficiency and high performance [C]∥ Proceedings of NAS. Zhang Jia Jie: [s.n.], 2009: 235-238.
[7] MA A, ZHANG M, ASANOVIC K. Way memorization to reduce fetch energy in instruction caches [C]∥ ISCA Workshop on Complexity Effective Design. Sweden: IEEE, 2001.
[8] XIE Z C, TONG D, CHENG X. WHOLE: a low energy I-cache with separate way history [C]∥ Proceedings of IEEE International Conference on Computer Design. California: IEEE, 2009:137-143.
[9] 龚帅帅,吴晓波,孟建熠,等. 基于历史链接关系的指令高速缓存低功耗方法[J].浙江大学学报:工学版,2011,45(3):467-471.
GONG Shuai-shuai, WU Xiao-bo, MENG Jian-yi, et al. Linking history based low-power instruction cache [J]. Journal of Zhejiang University: Engineering Science, 2011,45(3):467-471.
[10] PANWAR R, RENNELS D. Reducing the frequency of tag compares for low power I:cache design [C]∥ Proceedings of ISLPED. California: [s.n.], 1995:57-62.
[11] C-SKY microsystems. 32-bit high performance and low power embedded processor [EB/OL]. [2003-08-01]. http:∥ www.c-sky.com.
[12] BROOKS D, TIWARI V, MARTONOSI M. Wattch: a framework for architectural-level power analysis and optimizations [C]∥ Proceedings of the 27th Annual International Symposium on Computer Architecture. Vancouver: [s.n.], 2000:83-94. |
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