Please wait a minute...
浙江大学学报(工学版)
J4  2013, Vol. 47 Issue (1): 70-76    DOI: 10.3785/j.issn.1008-973X.2013.01.010
计算机技术﹑电信技术     
高灵敏度GNSS接收机频率合成器设计
尹喜珍1, 马成炎1,2, 叶甜春1, 肖时茂1, 于云丰1
1.中国科学院 微电子研究所,北京 100029; 2.杭州中科微电子有限公司,浙江 杭州 310053
Fractional-N frequency synthesizer for high sensitivity GNSS receiver
YIN Xi-zhen1, MA Cheng-yan1, 2, YE Tian-chun1, XIAO Shi-mao1, YU Yun-feng1
1.Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China；
2. Hangzhou Zhongke Microelectronics Limited Company, Hangzhou 310053, China
 全文: PDF  HTML
摘要：

为了提高全球卫星导航定位系统(GNSS)接收机的灵敏度,设计低相位噪声的小数频率合成器.通过分析灵敏度与相位噪声的关系,提出新的实现方案.该方案利用品质因数增强型可变电容减小压控振荡器(VCO)相位噪声,基于CMOS双D触发器单元的多模分频器和尾电流滤波的预分频降低带内相位噪声,充、放电流自校正且互补开关切换的电荷泵和带随机化抖动的ΣΔ调制器抑制杂散.该电路在0-18 μm CMOS工艺上实现.测试结果表明：提出的频率合成器能够接收所有的GNSS信号,输出的频率调谐范围达到58%,VCO增益变化小于±21%,当偏移频率为1 MHz时, 本振(LO)相位噪声低于-121 dB,最大功耗为117 mW.提出的小数频率合成器,已成功应用于高灵敏度GNSS接收机中,在GPS模式下灵敏度达到-157 dBm.
Abstract:

 A low phase noise fractional-N frequency synthesizer was designed to improve the sensitivity of global navigation satellite system(GNSS) receivers. A new implementation was proposed through analyzing the relation of sensitivity and phase noise. The scheme utilized enhanced quality factor varactor to reduce phase noise from VCO, a multi-modulus divider based on dual D flip-flop cell and prescaler with tail current filter to depress inband phase noise, and a charge/discharge current auto-calibration charge pump with complementary switches and random dithering ΣΔ modulator to restrain spurs. The circuit was implemented in 0-18 μm CMOS process. Measurement results indicated that the proposed synthesizer can receive all GNSS signals with a 58% frequency tuning range, and the variation of VCO gain (KVCO) was within ±21%. Local oscillator (LO) phase noise was lower than -121 dB at 1 MHz offset, and it consumed at most 117 mW power. The proposed fractional-N frequency synthesizer was successfully applied to high sensitivity GNSS receivers; the sensitivity was -157 dBm in GPS mode．
出版日期: 2013-01-01
:  TN 7962  
基金资助:

国家“863”高技术研究发展计划资助项目(2009AA011601), 国家“核高基”重大专项资助项目（2009ZX01031-002-008）.
通讯作者: 马成炎，男，研究员，博导.     E-mail: machengyan@casic.ac.cn
作者简介: 尹喜珍（1983-），男，博士生，从事频率合成器及时钟产生与恢复的研究.E-mail：yinxizhen@casic.ac.cn
服务　　
把本文推荐给朋友
加入引用管理器
E-mail Alert
RSS
作者相关文章　　

引用本文:

尹喜珍, 马成炎, 叶甜春, 肖时茂, 于云丰. 高灵敏度GNSS接收机频率合成器设计[J]. J4, 2013, 47(1): 70-76.

YIN Xi-zhen, MA Cheng-yan, YE Tian-chun, XIAO Shi-mao, YU Yun-feng. Fractional-N frequency synthesizer for high sensitivity GNSS receiver. J4, 2013, 47(1): 70-76.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2013.01.010    或    http://www.zjujournals.com/eng/CN/Y2013/V47/I1/70

［1］ WU Ling-juan, LU Wei-jun, YU Dun-shan. Research of weak signal acquisition algorithms for high sensitivity GPS receivers ［C］∥ Conference on PrimeAsia. Shanghai: IEEE, 2009: 173-176．
［2］ SOKOLOVA N, BORIO D, FORSSELL B, et al. Doppler rate measurements in standard and high sensitivity GPS receivers: theoretical analysis and comparison ［C］∥ Conference on IPIN. Hoenggerberg: IEEE, 2010: 19．
［3］ SCHON S, BIELENBERG O. On the capability of high sensitivity GPS for precise indoor positioning ［C］∥ 5th Workshop on Positioning, Navigation and Communication. Hannover: IEEE, 2008: 121-127．
［4］ 张朝杰, 金小军, 杨伟君,等. 高灵敏度微小卫星可变带宽接收机设计［J］. 浙江大学学报：工学版, 2011, 45(4): 588-590．
ZHANG Chao-jie, JIN Xiao-jun, YANG Weijun, et al. Design of variable loop bandwidth high sensitivity micro-satellite receiver ［J］. Journal of Zhejiang University: Engineering Science, 2011, 45(4): 588-590．
［5］ SERNA E P, THOMBRE S, VALKAMA M, et al. Local oscillator phase noise effects on GNSS code tracking ［J］. Inside GNSS, 2010, 5(6): 52-62．
［6］ RAZAVI B. RF microelectronics ［M］. America: Pearson Education, 1998: 33．
［7］ HEGAZI E, SJLAND H, ABIDI A A. A filtering technique to lower LC oscillator phase noise ［J］. IEEE Journal of SolidState Circuits, 2001, 36(12): 1921-1930．
［8］ LEVANTINO S, ROMANO L, PELLERANO S, et al. Phase noise in digital frequency dividers ［J］. IEEE Journal of SolidState Circuits, 2004, 39(5): 775-784．
［9］ VAUCHER C S, FERENCIC I, LOCHER M, et al. A family of lowpower truly modular programmable dividers in standard 0.35-μm CMOS technology ［J］. IEEE Journal of Solid-State Circuits, 2000, 35(7): 1039-1045．
［10］ RHEE W. Design of high-performance CMOS charge pumps in phaselocked loops ［C］∥ IEEE Proceedings of ISCAS. Orlando: IEEE, 1999, 2(7): 545-548．
［11］ GUPTA M, SONG B S. A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration ［J］. IEEE Journal of Solid-State Circuits, 2006, 41(12): 2842-2851．
［12］ GRAMEGNA G, MATTOS P G, LOSI M, et al. A 56 mW 23-mm2 single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1mm2 radio ［J］. IEEE Journal of SolidState Circuits, 2006, 41(3): 540-551．
［13］ WOO K, LIU Yong, NAM E, et al. Fast-lock hybrid PLL combining fractional-N and integer-N modes of differing bandwidths ［J］. IEEE Journal of Solid-State Circuits, 2008, 43(2): 379-389．
［14］ WU Ting, HANUMOLU P K, MAYARAM K, et al. Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers ［J］. IEEE Journal of Solid-State Circuits, 2009, 44(2): 427-435．
No related articles found!