| Electrical & Electronic Engineering |
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| A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic |
| ZENG Yong-hong, ZOU Xue-cheng, LIU Zheng-lin, LEI Jian-ming |
| Research Center for VLSI and Systems, Department of Electronic Science & Technology, Huazhong University of Science & Technology, Wuhan 430074, China |
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Abstract Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power consumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.
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Received: 09 March 2007
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