A new hardware stack of embedded processor was proposed to support seamless context switching and remove the performance loss during function call. The high-performance hardware stack is composed of data stack（DS）and returning stack (RS), and both of them are designed to be reconfigurable two-level buffer scheme to eliminate the overhead of process switching. DS utilizes two alternative general purpose register (GPR) to construct a new virtual GPR, which operates multiple data in/out stack in one cycle and performs switch automatically，hiding the performance cost of stack operations during program switching. RS preserves the function return address and corresponding instruction when function is called to eliminate the pipeline bubbles during the function returnes. Both DS and RS reuse partial memory space of scratchpad memory (SPM) as the second level buffers to provide support for user reconfiguration and sufficient buffer space for specified embedded software. Experiment results show that the performance is improved by over 10% while the power cost reduced by 2 % with the new hardware stack.
［1］ BOUYSSOUNOUSE B, SIFAKIS J. The artist roadmap for research and development ［C］∥ Embedded Systems Design. Secaucus, NJ, USA: SpringerVerlag New York, Inc, 2005:1-4． ［2］ YAU S S, KARIM F. An adaptive middleware for contextsensitive communications for realtime applications in ubiquitous computing environments ［J］. RealTime Systems, 2004, 26(1):29-61． ［3］ MAMIDIPAKA M, DUTT N. Onchip stack based memory organization for low power embedded architectures. design automation and test in Europe conference and exhibition ［C］∥ Proceedings of the Conference on Design, Automation and Test in Europe. Washington, DC, USA: IEEE Computer Society, 2003:11082． ［4］ JANG S J, CHUNG M K, KIM J,et al. Cache missaware dynamic stack allocation ［J］. Circuits and Systems, IEEE International Symposium on, 2007:3494-3497． ［5］ GHOSH A, GIVARGIS T. Cache optimization for embedded processor cores: an analytical approach ［J］. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2004, 9 (4):419-440． ［6］ARM Ltd. ARM11 Processor Introduction ［EB/OL］. ［2008-09-01］. http:∥www.arm.com/products/CPUs/ARM1176.html． ［7］ MIPS Technologies, Inc. MIPS 4KE Specification and User Guide ［EB/OL］. ［2008-09-01］. http:∥www.mips.com/products/cores/32-bit-cores/mips32-4ke/. ［8］ CSKY Microsystems. 32bit High Performance and Low Power Microprocessor CK510 ［EB/OL］. ［2003-08-01］. http:∥ www.c-sky.com．
