To meet the requirements for high linearity and out-of-band signal suppression in the RF communication front-end receiver, an RF receiver front-end operated at 5-6 GHz based on 130 nm SoI technology was proposed. The RF receiver front-end consisted of a low-noise amplifier (LNA) with bypass and out-of-band suppression, an RF switch, and a bandgap reference bias circuit. For a cascode-based LNA, an LC notch filter was used for input matching to achieve out-of-band suppression. In the bias circuit, a bandgap reference current source was used for temperature compensation for the bias of the LNA, thereby shielding the effect of the power supply ripple. The RF receiver front-end was processed and tested. Results showed that within the operating frequency band of 5–6 GHz, the gain of the receiver chip was 13.4?14.0 dB, input and output reflection coefficients were below ?10 dB, the minimum noise figure was 1.6 dB, the input 1 dB compression point was greater than ?4 dBm, and the input third-order intercept point was greater than +7 dBm. The amplifier was unconditionally stable across the entire frequency band. The DC power consumption was 30 mW at 2 V supply voltage, and the chip area was 0.56 mm2.
Haipeng FU,Zhiqiang CHENG. 5-6 GHz RF receiver front-end with 1.6 dB minimum noise figure and high out-of-band suppression. Journal of ZheJiang University (Engineering Science), 2024, 58(10): 2192-2198.
Fig.1Overall block diagram of RF receiver front-end
Fig.2RF switch topology
Fig.3LNA topology and input matching small signal model
Fig.4Schematic of low noise amplifier
Fig.5Bandgap reference circuit
Fig.6Comparison of bias voltage with and without temperature compensation
Fig.7Microscopic photo of chip
Fig.8Scattering parameter simulation and test results of low noise amplifier
Fig.9Simulation and test results of noise figure
Fig.10Simulation and test results of 1 dB compression point and input third-order intercept point
Fig.11Scattering parameter simulation and test results of bypass
Fig.12Scattering parameter simulation and test results of switch’s PA path
Fig.13Test results of 1 dB compression point for switch’s PA path
工艺
f /GHz
Gainmax/dB
NFmin/dB
IP1dB/dBm
IIP3/dBm
P/mW
A/mm2
FoM/GHz
180 nm CMOS[21]
0.1~2.0
17.5
2.9
?3.00
10.6
21.3
0.63
1.39
180 nm SoI[22]
1.0
10.7
1.3
3.00
22.0
50.0
0.67
1.34
GaAs pHEMT[23]
5.0~6.0
27.0
1.3
?13.00
—
240.0
4.29
1.64
130 nm CMOS[24]
5.0
25.5
1.9
?25.07
0
20.9
1.26
0.48
130 nm SoI（本研究）
5.0~6.0
14.0
1.6
?4.00
7.0
30.0
0.56
4.11
Tab.1Performance comparison of different low noise amplifiers
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