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浙江大学学报(工学版)
Journal of ZheJiang University (Engineering Science)  2019, Vol. 53 Issue (12): 2423-2430    DOI: 10.3785/j.issn.1008-973X.2019.12.021
Communication Technology     
High-speed analog-adaptive decision feedback equalizer with 0.18 μm CMOS technology
Yong-zheng ZHAN(),Qing-sheng HU*()
Institute of RF- and OE-ICs, Southeast University, Nanjing 210096, China
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Abstract  

A 2-tap analog-adaptive decision feedback equalizer (DFE) was designed using 0.18 μm CMOS technology for high-speed backplane communication. Half-rate architecture was adopted to improve the speed and reduce the power. And analog least-mean-square adaptive circuit composed of multiplier and integrator was designed. In order to improve the effect of adaptive algorithm, LMS analog circuit was optimized, which not only ensured the requirement of the adaptive convergence and stability, but also obtained the smaller integral error to output the stable bias voltage for integrator. The whole chip area including pads was 0.378 mm2. The test results show that DFE can compensate 12 dB channel loss at 4 GHz when adaptive circuit was turned on, and the vertical opening and horizontal opening reached 275.5 mV and 72 ps, respectively, which was significantly better than that when it was turned off. The power consumption was 49.9 mW at the supply voltage of 1.8 V and the rate of 8 Gb/s. The designed analog-adaptive DFE circuit is more suitable for high-speed communication link systems of 25 G and above.

Key words： decision feedback equalizer (DFE)      half-rate      least-mean-square (LMS)      integrator     
Received: 06 November 2018      Published: 17 December 2019
CLC:  TN 432  
Corresponding Authors: Qing-sheng HU     E-mail: sdzyz1989@163.com;qshu@seu.edu.cn
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Yong-zheng ZHAN
Qing-sheng HU
Cite this article:

Yong-zheng ZHAN,Qing-sheng HU. High-speed analog-adaptive decision feedback equalizer with 0.18 μm CMOS technology. Journal of ZheJiang University (Engineering Science), 2019, 53(12): 2423-2430.

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http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2019.12.021     OR     http://www.zjujournals.com/eng/Y2019/V53/I12/2423


采用0.18 μm CMOS工艺的高速模拟自适应判决反馈均衡器

采用0.18 μm CMOS工艺设计实现适用于高速背板通信的2抽头模拟自适应判决反馈均衡器(DFE). 采用半速率结构提高电路工作速度, 降低功耗, 并设计由乘法器和积分器构成的模拟最小均方(LMS)自适应电路. 为了改善自适应算法的效果, 对模拟LMS电路进行优化设计, 使其既满足自适应算法的收敛性和稳定性要求, 又能获得较小的积分误差, 并且积分器能够输出稳定的偏置电压. 包括整个焊盘在内的芯片面积为0.378 mm2. 测试结果表明：电路自适应开启时能够对4 GHz损耗为12 dB的信道进行有效补偿, 且垂直张开度和水平张开度分别达到275.5 mV和72 ps, 均衡效果明显优于自适应关闭状态. 当电源电压为1.8 V、工作速度为8 Gb/s时，电路的功耗为49.9 mW. 所设计的模拟自适应DFE电路更适用于25 G及以上的高速通信链路系统.


关键词： 判决反馈均衡器(DFE),  半速率,  最小均方(LMS),  积分器 
Fig.1 Block diagram of sign-sign least mean square (S-S LMS) algorithm
Fig.2 Block diagram of analog least mean square (LMS) circuit
Fig.3 Analog-adaptive half-rate decision feedback equalizer (DFE)
Fig.4 D flip-flop (DFF) schematic
Fig.5 Addition-multiplication circuit schematic
Fig.6 Gilbert multiplier schematic
Fig.7 Integrator circuit schematic
Fig.8 Frequency response of designed multiplier
Fig.9 Convergence characteristics of LMS algorithm under different integral time constants
Fig.10 Simulation results of adaptive equalization effects
Fig.11 Chip micrograph
Fig.12 Chip measurement scheme and instruments
Fig.13 Measurement results for 8 Gb/s 2-tap analog-adaptive DFE
来源 CMOS工艺 v/(Gb·s-1) 结构 DFE自适应 S/mm2 P/mW L/dB U/V
注：1)包含时钟及数据恢复(clock and data recovery, CDR)的功耗
本文 0.18 μm 8.00 半速率DFE 模拟 0.378 49.9 12.0 1.8
文献[14] 0.18 μm 6.25 半速率DFE 数字 0.33 49.5 9.7 1.8
文献[15] 40 nm 15.00 CTLE+半速率预处理DFE 模拟 2.03 72.5 23.0 1.1
文献[16] 0.13 μm 10.00 FFE+全速率DFE 模拟 5.52 452.01) 16.3 1.2
Tab.1 Performance comparison among different adaption equalizers
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