Please wait a minute...
浙江大学学报(工学版)
J4  2011, Vol. 45 Issue (6): 1038-1042    DOI: 10.3785/j.issn.1008-973X.2011.06.012
无线电电子学、电信技术     
N型LDMOS器件在关态雪崩击穿条件下的退化
郭维, 丁扣宝, 韩成功, 朱大中, 韩雁
浙江大学 信息与电子工程学系,浙江 杭州 310027
Off-state avalanche breakdown induced degradation in
NLDMOS devices
GUO Wei, DING Kou-bao, HAN Cheng-gong, ZHU Da-zhong, HAN Yan
Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
 全文: PDF  HTML
摘要：

针对功率开关管在未箝位电感性开关转换时会反复发生雪崩击穿,引起器件参数退化的问题,对一种20 V N型横向双扩散MOS器件(NLDMOS)在关态雪崩击穿条件下导通电阻的退化进行研究.通过恒定电流脉冲应力测试、TCAD（technology computeraided design）仿真和电荷泵测试,分析研究导通电阻退化发生的区域及退化的微观机理,并针对实验结果提出2种退化机制：(1) NLDMOS漂移区中的空穴注入效应,这种机制会在器件表面产生镜像负电荷,造成开态导通电阻Ron的减少；(2)漂移区中的表面态增加效应,这种机制会造成载流子迁移率的下降,引起Ron的增加.这2种机制都随着雪崩击穿电流的增加而增强.
Abstract:

Degradation behaviors of 20 V NLDMOS operated under off-state avalanche breakdown condition were presented to study the reliability issue caused by repeatedly avalanche breakdown of the N-type lateral double diffusion MOS transistor（NLDMOS）under unclamped inductive switching. The on-resistance degradation region and micro-mechanism were investigated by the analysis of constant current pulse stress tests, technology computer-aided design (TCAD) simulation and charge pumping measurements. Two different degradation mechanisms are identified: (1) The positive oxidetrapped charge accumulation effect in the N-type drift region induces the mirrored negative charges in the device surface, so the on-resistance decreases;(2)The surface states formation effect reduces the channel electron mobility, so the onresistance increases. The both mechanisms are enhanced with the increasing avalanche breakdown current.
出版日期: 2011-07-14
:  TN 40  
基金资助:

浙江省科学技术厅科技计划资助项目（2006C11007）.
通讯作者: 丁扣宝，男，副教授.     E-mail: dingkb@zju.edu.cn
作者简介: 郭维（1973—），男，博士生，从事混合信号处理电路、功率集成电路、电源管理电路研究.
服务　　
把本文推荐给朋友
加入引用管理器
E-mail Alert
作者相关文章　　

引用本文:

郭维, 丁扣宝, 韩成功, 朱大中, 韩雁. N型LDMOS器件在关态雪崩击穿条件下的退化[J]. J4, 2011, 45(6): 1038-1042.

GUO Wei, DING Kou-bao, HAN Cheng-gong, ZHU Da-zhong, HAN Yan. Off-state avalanche breakdown induced degradation in
NLDMOS devices. J4, 2011, 45(6): 1038-1042.

链接本文:

https://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2011.06.012    或    https://www.zjujournals.com/eng/CN/Y2011/V45/I6/1038

［1］ CHEN J F, LEE J R, WU K M, et al. Offstate avalanchebreakdowninduced onresistance degradation in lateral DMOS transistors［J］. IEEE Electron Devices Letters, 2007, 28(11): 1033-1035.
［2］ MOENS P, VAN DEN B. Characterization of total safe operation area of lateral DMOS transistors ［J］. IEEE Transactions on Device and Materials Reliability, 2006, 16(3): 349-357.
［3］ BRISBIN D, LINDORFER P, CHAPARALA P. Anomalous safe operating area and hot carrier degradation of NLDMOS devices［J］. IEEE Transactions on Device and Materials Reliability, 2006, 6(3): 364-370.
［4］ MOENS P, BOSCH D V, KEUKELEIRE C, et al. Hot hole degradation effects in lateral nDMOS transistors［J］. IEEE Transaction on Electron Devices,2004, 51(10): 1704-1710.
［5］ WU K M, CHEN J F, SU Y K, et al. Anomalous reduction of hotcarrierinduced onresistance degradation in ntype DEMOS transistors［J］. IEEE Transactions on Device and Materials Reliability, 2006, 6(3): 371-376.
［6］ MARBELL M N. CHEREPKO N, SHWANG S V, et al. Effects of dummy gate on breakdown and degradation of LDMOSFETs［J］. IEEE Transactions on Device and Materials Reliability, 2008, 8(1): 193-202.
［7］ MOENS P, BOSCH D V, GROESENEKEN G. Hotcarrier degradation phenomena in lateral and vertical DMOS transistors［J］. IEEE Transaction on Electron Devices, 2004, 51(4): 623-628.
［8］ CHEN J F, LEE J R, WU K M, et al. Mechanism and improvement of onresistance degradation induced by avalanche breakdown in lateral DMOS transistors ［J］. IEEE Transactions on Electron Devices, 2008, 55(8): 2259-2262.
No related articles found!