Please wait a minute...
浙江大学学报(工学版)
J4  2009, Vol. 43 Issue (5): 860-863    DOI: 10.3785/j.issn.1008-973X.2009.05.014
自动化技术、计算机技术     
基于多阈值技术的低功耗优先编码器设计
胡晓慧1,张慧熙2,沈继忠1,3
（1.浙江大学城市学院,信息与电气工程学院,浙江 杭州310015；2.杭州师范大学 钱江学院,浙江 杭州 310012； 3.浙江大学 信息与电子工程学系,浙江 杭州 310027）
Design of low power priority coder based on multi-threshold technique
HU Xiao-hui1, ZHANG Hui-xi2, SHEN Ji- zhong1,3
(1. School of Information and Electrical Engineering, Zhejiang University City College, Hangzhou 310015, China;
2. College of Qianjiang, Hangzhou Normal University, Hangzhou 310012, China;
3. Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China)
 全文: PDF(475 KB)   HTML
摘要：

多阈值CMOS技术是一种新的降低电路功耗的设计技术.根据多阈值CMOS电路设计原理,设计了多阈值组合逻辑单元电路,并将多阈值技术与冗余抑制技术结合起来,设计了多阈值优先编码器,通过将高阈值NMOS管的控制信号用较高优先权的输入信号进行控制,抑制了优先编码器的冗余现象,控制了电路的漏电流,且无须增加控制信号.采用0.18μm工艺参数进行模拟,结果表明,所设计的多阈值优先编码器具有正确的逻辑功能,在相同的参数条件和输入信号下,与已有的冗余抑制优先编码器相比,节省约19％的功耗；与传统的优先编码器相比,节省了约49％的功耗.
Abstract:

Multi-threshold CMOS is a new technique to reduce the power dissipation. According to the principle of multi-threshold CMOS (MT-CMOS), multi-threshold combinational  logic unit circuits were designed, and a low power priority coder was designed by MT-CMOS and redundancy-restraining technique. The high threshold voltage NMOS devices were  controlled by higher priority inputs to restrain the redundancy of the priority encoder and reduce the leakage current without any other controlling signal. Simulation based on  the 0.18 μm standard suggested that the designed multi-threshold priority coder not only had correct logic function, but also reduced the leakage power and saved about 19%  power compared with the existing redundancy-restraining priority coder, and saved 49% power compared with the conventional priority coder．
出版日期: 2009-11-18
:  TN432  
基金资助:

浙江大学城市学院教师科研基金资助项目（J-09012）.
作者简介: 胡晓慧（1982-），女，安徽淮南人，讲师，主要从事低功耗集成电路设计研究.
服务　　
把本文推荐给朋友
加入引用管理器
E-mail Alert
RSS
作者相关文章　　

引用本文:

胡晓慧, 张慧熙, 沈继忠. 基于多阈值技术的低功耗优先编码器设计[J]. J4, 2009, 43(5): 860-863.

HU Xiao-Hui, ZHANG Hui-Xi, CHEN Ji-Zhong. Design of low power priority coder based on multi-threshold technique. J4, 2009, 43(5): 860-863.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2009.05.014    或    http://www.zjujournals.com/eng/CN/Y2009/V43/I5/860

［1］ GHANI T, MISTRY K, PACKAN P, et al. Scaling challenges and device design requirements for high performance sub-50nm gate length planar CMOS transistors ［C］∥ Proceedings  of International Symposium on VLSI Technology, Systems, and Applications. Honolulu: ［s.n.］, 2000: 174175．
［2］ KANG S M S. Elements of low power design for integrated systems ［C］∥ Proceedings of the 2003 International Symposium on Low Power Electronics and Design. Seoul: ACM,  2003: 205210．
［3］ LIU Zhi-yu, KURSUN V. Charge recycling MTCMOS for low energy active/sleep mode transitions ［C］∥ IEEE International Symposium on Circuits and Systems. New Orleans: IEEE,  2007: 13891392.
［4］ ANIS M, AREIBI S, ELMASRY M. Design and optimization of multithreshold CMOS (MT CMOS) circuits ［J］. IEEE Transactions on Computer-Aided Design of Integrated Circuits and  Systems, 2003, 22(10): 13241342．
［5］ KHANDELWAL V, SRIVASTAVA A. Leakage control through fine-grained placement and sizing of sleep transistors ［J］. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems, 2007, 26(7):12461255．
［6］ KAO J T, CHANDRAKASAN A P. Dual-threshold voltage techniques for low-power digital circuits ［J］. IEEE Journal of Solid-State Circuits, 2000, 35(7): 10091018．
［7］ USAMI K, KAWABE M, SETA K, et al. Automated selective multi-threshold design for ultra-low standby applications ［C］∥ Proceedings of the 2002 International Symposium on  Low Power Electronics and Design. Monterey: ACM, 2002: 202206．
［8］ 卢仰坚,吴训威. 抑制冗余优先编码器的逻辑设计［J］. 浙江大学学报：理学版, 2001, 28(4): 468472．
LU Yang-jian, WU Xun-wei. The logic design of priority encoder with redundant-restraining ［J］. Journal of Zhejiang University: Science Edition, 2001, 28(4): 468472．
No related articles found!