Please wait a minute...
浙江大学学报(工学版)
J4  2013, Vol. 47 Issue (5): 837-842    DOI: 10.3785/j.issn.1008-973X.2013.05.015
电气工程、电信技术     
基于模块化单元的测试结构阵列设计及其应用
张波,潘伟伟,叶翼,郑勇军,史峥,严晓浪
浙江大学 超大规模集或电路设计研究所, 浙江 杭州 310027　　
Design and application of test structure array based on modular unit
ZHANG Bo, PAN Wei-wei, YE Yi, ZHENG Yong-jun, SHI Zheng, YAN Xiao-lang
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China)
 全文: PDF  HTML
摘要：

针对纳米级半导体制造工艺中传统测试芯片掩模面积利用率低的问题,提出一种基于模块化单元的可扩展成品率测试结构阵列设计方法. 基于45 nm CMOS制造工艺分别实现32×32和64×64  2个大规模的测试结构阵列, 模块化单元的有效面积利用率达7931%和708%|流片后通过测试数据的分析能够发现通孔缺失、通孔尺寸变大以及大尺寸缺陷导致金属缺失等工艺缺陷问题.试验结果同时表明,该方法将传输门器件和测试结构组合成模块化单元； 不仅能够实现对测试结构的四端测量, 保证测试结果的正确性, 并且能够减小成品率测试芯片的掩模面积．
Abstract:

A modular unit based design method of scalable test structure array is presented, aiming to increasing mask utilization ratio of test chips in nanometer scale IC manufacturing. Implemented in 45 nm CMOS technology, two large-scale test structure arrays, with 32×32 and 64×64 units respectively, had been designed and fabricated as the experiments. By combining the device-under-test (DUT) and the transmission gates into one standard modular unit, the area utilization reached 79.31% and 70.8% for these experiments. Process defects such as via-induced metal loss were reported after testing data analysis. The results demonstrated that the process window could be sufficiently tracked with those arrays, which further proves the accuracy and effectiveness of the presented design method.
出版日期: 2013-05-01
:  TN 43  
基金资助:

 国家自然科学基金资助项目(61106034);国家重大科技专项资助项目(2009ZX02023-004-1).
通讯作者: 史峥, 男, 副教授.     E-mail: shiz@vlsi.zju.edu.cn
作者简介: 张波(1984-), 男, 博士生, 从事集成电路成品率提升科研工作. E-mail: zhangbo@vlsi.zju.edu.cn．
服务　　
把本文推荐给朋友
加入引用管理器
E-mail Alert
RSS
作者相关文章　　

引用本文:

张波,潘伟伟,叶翼,郑勇军,史峥,严晓浪. 基于模块化单元的测试结构阵列设计及其应用[J]. J4, 2013, 47(5): 837-842.

ZHANG Bo, PAN Wei-wei, YE Yi, ZHENG Yong-jun, SHI Zheng, YAN Xiao-lang. Design and application of test structure array based on modular unit. J4, 2013, 47(5): 837-842.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2013.05.015    或    http://www.zjujournals.com/eng/CN/Y2013/V47/I5/837

［1］ KETCHEN M B, BHUSHAN M, COSTRINI G. Addressable arrays implemented with one metal level for MOSFET and resistor variability characterization ［C］∥ IEEE International Conference on Microelectronic Test Structures. New York: IEEE, 2009: 13-18．
［2］ MIZUMURA A, SUZUKI T, ARIMA T, et al. A study of variation in characteristics and subthreshold humps for 65-nm SRAM using newly developed SRAM cell array test structure［C］∥ IEEE International Conference on Microelectronic Test Structures. Atsugi: IEEE, 2008: 8-10．
［3］ HAFKEMEYER K M, DOMDEY A, SCHROEDER D, et al. Array test structure for ultra-thin gate oxide degradation issues［C］∥ IEEE International Conference on Microelectronic Test Structures. New York: IEEE, 2009: 85-90．
［4］ TIAN Weidong, STEINMANN P, BEACH E, KHAN I, et al. Mismatch characterization of a high precision resistor array test structure［C］ ∥ IEEE International Conference on Microelectronic Test Structures. Atsugi: IEEE, 2008: 11-16．
［5］ RIGAUD F, PORTAL J M, AZIZA H, et al. Mixed test structure for soft and hard defect detection［C］∥ IEEE International Conference on Microelectronic Test Structures. Atsugi: IEEE, 2008: 52-55．
［6］ DOMDEY A, HAFKEMEYER, K M, SCHROEDER D, et al. Reliability analysis of gate dielectrics by applying array test structures and automated test systems ［J］. NORCHIP, 2009, 15．
［7］ DOONG K Y, BORDELON T J, HUNG Lien-Jung, et al. Field-configurable test structure array (FC-TSA): enabling design for monitor, model, and manufacturability ［J］. Semiconductor Manufacturing, IEEE Transactions, 2008, 21（ 2）: 169-179．
［8］ SMITH B, ARRIORDAZ A, KOLAGUNTA V, et al. A novel biasing technique for addressable parametric arrays ［J］. Semiconductor Manufacturing, IEEE Transactions , 2009, 22 （1）: 134-145．
［9］ HESS C, SQUCCIARINI M, SHIA Yu, et al. High density test structure array for accurate detection and localization of soft fails［C］∥ IEEE International Conference on. Microelectronic Test Structures. Atsugi: IEEE, 2008: 131-136．
［10］ KARTHIKEYAN M, GASASIRA A, FOX S, et al, Development and use of small addressable arrays for process window monitoring in 65nm manufacturing［C］∥ IEEE International Conference on Microelectronic Test Structures. Tokyo: IEEE, 2007: 135-139．
［11］ YAMAMOTO M, ENDO H, Masuda H, et al. Development of a large-scale TEG for evaluation and analysis of yield and variation［J］. IEEE Transactions on Semiconductor Manufacturing, 2004, 17（2）: 111-122．
［12］ SHIBUYA A, MORI S, KUSAKABE T, et al. Quantitative evaluation of line width roughness-effect on mosfet electrical properties using a large array test structure ［C］∥ International Symposium on VLSI Technology, Systems and Applications. Hsinchu, Taiwan: IEEE, 2007: 12.
［13］ PAN Weiwei, REN Jie, ZHENG Yongjun, et al. Using NMOS transistors as switches for accuracy and area-efficiency in large-scale addressable test array ［C］∥ 12th International Symposium on Quality Electronic Design.  Santa Clara, California: IEEE, 2011: 16．
［14］ GABRYS A, GREIG W, WEST A J, et al. Highly automated test chip layout and test plan development for parametric electrical test［C］∥ IEEE International Conference on Microelectronic Test Structures. Atsugi, Japan: IEEE, 2008: 96-100．
［15］ ZHANG Bo, PAN Wei, ZHENG Yong-jun, et al. A fully automated large-scale addressable test chip design with high reliability［C］∥ 20th European Conference on. Circuit Theory and Design .Linkoping, Sweden: IEEE, 2011: 61-64．
No related articles found!