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浙江大学学报(工学版)
J4  2011, Vol. 45 Issue (3): 462-466    DOI: 10.3785/j.issn.1008-973X.2011.03.011
电气工程     
基于高速缓存资源共享的TLB设计方法
徐鸿明,孟建熠,严晓浪,葛海通
浙江大学 超大规模集成电路设计研究所,浙江 杭州 310027
Translation look-aside buffer design method based on
cache resource reusing
XU Hong-ming, MENG Jian-yi, YAN Xiao-lang, GE Hai-tong
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
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摘要：

针对嵌入式处理器中旁路转换缓冲（TLB）功耗和面积显著的问题，提出一种共享高速缓存硬件资源的低功耗TLB设计方法，消除了传统方法中TLB存储器的硬件资源及静态功耗.该方法通过设立两级TLB低功耗架构和缓存地址映射表，有效减少TLB的访问次数，降低了功耗；利用高速缓存的结构特性动态扩展TLB表项，扩大对物理内存的映射范围，提升TLB命中率.进一步提出了一种复用缓存替换策略的TLB表项的编码加锁方法，减少页面抖动，缓和TLB表项与指令、数据的资源冲突.实验结果表明:与传统的TLB设计相比，应用本方法的嵌入式处理器的功耗下降28.11%，面积减少21.58%.
Abstract:

A new translation look-aside buffer （TLB） design method with cache resource reusing was proposed  for reducing the power consumption and area cost in the embedded processor. This method bases on a two-level TLB architecture and an address mapping table of cache, and decreases the frequency of TLB accesses with low power consumption. The dynamic expansion mechanism of TLB entry with cache resource reusing enlarges the mapping range of physical address for high TLB hit rate. Moreover, a locking method of TLB entry was  proposed to balance the resource hazard between TLB entry and instruction/data in cache. Comparing with the traditional TLB design, experiments showed that the proposed method reduced the power consumption and the area cost of embedded processor by 28.11% and 21.58% respectively.
出版日期: 2012-03-16
:  TP 302.2  
基金资助:

国家自然科学基金资助项目( 60720106003 ).
通讯作者: 孟建熠，男，博士后.     E-mail: mengjy@vlsi.zju.edu.cn
作者简介: 徐鸿明（1984-），男，浙江绍兴人，硕士生，从事高性能低功耗嵌入式处理器的设计与研究.E-mail:xuhongming0301@gmail.com
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引用本文:

徐鸿明,孟建熠,严晓浪,葛海通. 基于高速缓存资源共享的TLB设计方法[J]. J4, 2011, 45(3): 462-466.

XU Hong-ming, MENG Jian-yi, YAN Xiao-lang, GE Hai-tong. Translation look-aside buffer design method based on
cache resource reusing. J4, 2011, 45(3): 462-466.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2011.03.011    或    http://www.zjujournals.com/eng/CN/Y2011/V45/I3/462

［1］ CHOI J H, LEE J H, JEONG S W, et al. A low power TLB structure for embedded systems ［J］. Computer Architecture Letters, 2002, 1(1) : 3．
［2］ LIN Chisheng, CHANG Juichuan, LIU Binda. A lowpower precomputationbased fully parallel contentaddressable memory ［J］. IEEE Journal of SolidState Circuits, 2003, 38(4): 654-662．
［3］ KADAYIF I, SIVASUBRAMANIAM A, KANDEMIR M. Generating physical addresses directly for saving instruction TLB energy ［C］∥ Proceedings of the 35th Annual IEEE/ACM International Symposium on Microar chitecture. Istanbul: IEEE, 2002: 185-196．
［4］ LEE J H, PARK G H, PARK S B. A selective filterbank TLB system ［C］∥ Proceedings of the 2003 International Symposium on Low Power Electronics and Design. Seoul: IEEE, 2003: 312-317．
［5］ CHANG Yenjen. An ultra lowpower TLB design ［C］∥ Proceedings of the Conference on Design, Automation and Test in Europe. Munich: IEEE, 2006: 1-6．
［6］ MIN J H, LEE J H, JEONG S W. A selectively accessing TLB for high performance and lower power consumption ［C］∥ Proceedings of IEEE AsiaPacific Conference on ASIC. ［S.l.］: IEEE,2002: 45-48．
［7］ CHANG Yenjen, LAN Maofeng. Two new techniques integrated for energyefficient TLB design ［J］. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007, 15(1): 13-23．
［8］ LEE J H, LEE J S, KIM S D. A dynamic TLB management structure to support different page sizes ［C］∥ Proceedings of the Second IEEE Asia Pacific Conference on ASICs.Korea: IEEE, 2000:299-302．
［9］ LEE J H, WEEMS C, KIM S D. Selective block buffering TLB system for embedded processors ［J］ Computers and Digital Techniques,2005, 152(4):507-516．
［10］ CSKY Microsystems. 32bit High Performance and Low Power Embedded Processor ［EB/OL］. 2003-07-10.http:∥www.c-sky.com．
［11］ 刘坤杰, 游海亮, 严晓浪, 等. 面向嵌入式应用的内存管理单元设计 ［J］. 浙江大学学报:工学版, 2007, 41(7): 1078-1082．
LIU Kunjie, YOU Hailiang, YAN Xiaolang, et al. Design of application specific embedded memory management unit ［J］. Journal of Zhejiang University: Engineering Science, 2007, 41(7): 1078-1082.
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