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J4  2010, Vol. 44 Issue (6): 1067-1072    DOI: 10.3785/j.issn.1008-973X.2010.06.003
自动化技术、计算机技术     
基于调试异常模型的嵌入式处理器片上调试设计
刘鹏1, 钟耿1, 徐国柱1,2, 邬可俊1
1.浙江大学 信息与电子工程学系, 浙江 杭州310027; 2.杭州士兰微电子股份有限公司,浙江 杭州 310012
On-chip debug design based on debug exception model for embedded processor
LIU Peng1, ZHONG Geng1, XU Guo-zhu1,2, WU Ke-jun1
1. Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China;
2. Hangzhou Silan Microelectronics CO.,LTD, Hangzhou 310012, China
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摘要:

针对调试的可移植性, 建立同流水相关的精确调试异常模型, 模型通过增加调试中断、单步、软硬件断点等精确调试异常的产生和处理机制、片外调试存储空间以及基于JTAG(joint test action group)的快速通信协议, 实现一种通过JTAG接口的嵌入式处理器核的片上调试方案. 该调试模型在嵌入式处理器RISC32E核的应用实现表明,它具有良好的可观察性和可控制性,并且该模型的应用不局限于六级流水结构的微处理器,还可以方便地推广到其他流水结构的微处理器.对比调试过程中的一些基本调试操作开销,该调试方案具有较高的调试效率.

Abstract:

A general precise debug exception model based on pipeline was established with portability, which provides a strategy for on-chip debug by adding generation and processing mechanism of precise debug exceptions, such as debug interrupt, step, hardware/software breakpoints, etc., in addition of a segment of offchip debug memory and a fast transfer method through joint test action group(JTAG) port. The implementation of the proposed model on an embedded processor RISC32E shows that it meets the requirements of observability and controllability. The above description should not be taken as limiting the utilization of the model which is defined by the sixpipeline microprocessor. The model can be easily transplanted onto other microprocessors which have various modifications of pipeline. The proposed strategy has great efficiency of debugging in the case of comparison of some basic debugging operation overhead.

出版日期: 2010-07-16
:  TP 316  
作者简介: 刘鹏(1970—),男,陕西铜川人,副教授,主要从事计算机体系结构、集成电路设计和并行处理等研究.
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引用本文:

刘鹏, 钟耿, 徐国柱, 邬可俊. 基于调试异常模型的嵌入式处理器片上调试设计[J]. J4, 2010, 44(6): 1067-1072.

LIU Feng, ZHONG Geng, XU Guo-Zhu, WU Ge-Dun. On-chip debug design based on debug exception model for embedded processor. J4, 2010, 44(6): 1067-1072.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2010.06.003        http://www.zjujournals.com/eng/CN/Y2010/V44/I6/1067

[1] HOPKINS A B T, MCDONALDMAIER K D. Debug support strategy for systemsonchips with multiple processor cores [J]. IEEE Transactions on Computers, 2006, 55(2): 174184.

[2] CROUCH A L. Designfortest for digital IC’s and embedded core systems [M]. New Jersey: Prentice Hall, 1999.

[3] MAIER K D. Onchip debug support for embedded SystemsonChip[C]∥Proceedings of the 2003 International Symposium on Circuits and Systems. New York,:[s.n.],2003: 565568.

[4] STALLMAN R, PESCH R H. Debugging with GDB [M]. 9th ed. Boston: The Free Software Foundation, 2004.

[5] 吴皓,刘鹏.基于JTAG的DSP处理器嵌入式调试接口设计[J].计算机工程,2005,31(1): 228230.

WU Hao, LIU Peng. Implementation of debug interface of DSP processor based on JTAG architecture[J]. Computer Engineering, 2005, 31(1): 228230.(in Chinese)

[6] 胡学良,张春,王志华.JTAG技术的发展和应用综述[J].微电子学,2005,35(6): 624630.

HU Xueliang, ZHANG Chun, WANG Zhihua. An overview of JTAG technology: development and application [J]. Microelectronics, 2005, 35(6): 624630. (in Chinese)

[7] 黄海林,范东睿,许彤,等.嵌入式处理器在片调试功能的设计与实现[J].计算机辅助设计与图形学学报,2006,18(7): 10051010.

HUANG Hailin, FAN Dongrui, XU Tong, et al. Design and implementation of onchip debug features in embedded processor [J]. Journal of ComputerAided Design & Computer Graphics, 2006, 18(7): 10051010. (in Chinese)

[8] 郑德春,姚庆栋,刘鹏,等.嵌入式模拟器中的JTAG应用[J].浙江大学学报:工学版,2006,40 (1): 2024.

ZHENG Dechun, YAO Qingdong, LIU Peng, et al. JTAG application in embeddedin circuit emulator\
[J\]. Journal of Zhejiang University:Engineering Science, 2006, 40(1): 2024.(in Chinese)

[9] MELEAR C. Using background modes for testing, debugging and emulation of microcontrollers[C] ∥ Proceedings of the 1997 WESCON Conference.San Jose: WESCON ,1997: 9097.

[10] IEEE Std 1149.12001 IEEE standard test access port and boundaryscan architecture[S]. New York: The Institute of Electrical and Electronics Engineers, Inc., 2001.

[11] MANOHAR R, NYSTORM M, MARTIN A J. Precise exceptions in asynchronous processors[C] ∥Proceedings of the 19th Conference on Advanced Research in VLSI. Salt Lake City:[s.n.], 2001: 1628.

[12] PATTERSON D A, HENNESSY J. Computer organization and design: the hardware/software interface [M]. 3rd ed. Beijing: China Machine Press, 2006.

[13] 刘鹏,钟耿,徐国柱,等.一种微处理器调试方法及所用的微处理器调试模块:中国,200810060713.1[P],20080425.

LIU Peng, ZHONG Geng, XU Guozhu, et al. A debug method and its debug unit of embedded processor: China, 200810060713.1[P], 20080425.

[14] MIPS Technologies Inc. EJTAG Specication[OL/EB]. [20030507]. http:∥ www.mips.com.

[15] XIAO Zhibin, LIU Peng, YAO Yingbiao, et al. Optimizing pipeline for a RISC processor with multimedia extension ISA [J]. Journal of Zhejiang University Science A, 2006, 7(2): 269274.

[16] JIANG Guofan, LIU Peng, GU Xiongli, et al. RISC32E: an extensible 32bit embedded microprocessor IP core[C] ∥China Symposium of Circuit and Systems. Guangzhou, China:[s.n.], 2007: 471476.

[17] 江国范.异质媒体双发射处理器的设计研究[D].杭州:浙江大学,2008.

JIANG Guofan. Research on the heterogeneous media dualissue processor design [D]. Hangzhou: Zhejiang University, 2008.

[18] 钟耿.嵌入式系统片上调试研究[D].杭州:浙江大学,2008.

ZHONG Geng. Research on onchip debug for embedded system [D]. Hangzhou: Zhejiang University, 2008.

[19] 王玥.嵌入式SoC可调试设计的研究[D].杭州:浙江大学,2007.

WANG Yue. Debug design for Embedded SoC [D]. Hangzhou: Zhejiang University, 2007.

[20] 成杏梅,刘鹏,钟耿,等.嵌入式MPSoC的调试功能实现[J].计算机辅助设计与图形学学报,2008,20(4): 438445.

CHENG Xingmei, LIU Peng, ZHONG Geng, et al. Debug function implementation for embedded MPSoC[J]. Journal of ComputerAided Design & Computer Graphics, 2008, 20(4):438445. (in Chinese)

[21]  DENX Software Engineering, the Embedded Linux Development Kit[CP/OL].20070129. http:∥mirror.switch.ch/ftp/mirror/eldk/eldk/4.1.

[22] SGI. The Linux Test Project [CP/OL].20070331.http:∥ltp.sourceforge.net.

[23] 张伟,李兆麟,张闯,等.一种基于JTAG的嵌入式微处理器片上可调试系统[J].计算机工程与应用,2004,40(12): 14,51.

ZHANG Wei, LI Zhaolin, ZHANG Chuang, et al. An onchip debug system based on JTAG for embedded microprocessors [J]. Computer Engineering and Applications, 2004, 40(12):14, 51.(in Chinese)

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