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Front. Inform. Technol. Electron. Eng.  2012, Vol. 13 Issue (6): 460-471    DOI: 10.1631/jzus.C1100273
    
High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility
Hossein Aghababa, Behjat Forouzandeh, Ali Afzali-Kusha
Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran 14395, Iran
High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility
Hossein Aghababa, Behjat Forouzandeh, Ali Afzali-Kusha
Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran 14395, Iran
 全文: PDF 
摘要： We propose a modeling methodology for both leakage power consumption and delay of basic CMOS digital gates in the presence of threshold voltage and mobility variations. The key parameters in determining the leakage and delay are OFF and ON currents, respectively, which are both affected by the variation of the threshold voltage. Additionally, the current is a strong function of mobility. The proposed methodology relies on a proper modeling of the threshold voltage and mobility variations, which may be induced by any source. Using this model, in the plane of threshold voltage and mobility, we determine regions for different combinations of performance (speed) and leakage. Based on these regions, we discuss the trade-off between leakage and delay where the leakage-delay-product is the optimization objective. To assess the accuracy of the proposed model, we compare its predictions with those of HSPICE simulations for both basic digital gates and ISCAS85 benchmark circuits in 45-, 65-, and 90-nm technologies.
关键词： High-performance circuit;  Low-leakage circuit;  Manufacturing process variation;  CMOS integrated circuit    
Abstract: We propose a modeling methodology for both leakage power consumption and delay of basic CMOS digital gates in the presence of threshold voltage and mobility variations. The key parameters in determining the leakage and delay are OFF and ON currents, respectively, which are both affected by the variation of the threshold voltage. Additionally, the current is a strong function of mobility. The proposed methodology relies on a proper modeling of the threshold voltage and mobility variations, which may be induced by any source. Using this model, in the plane of threshold voltage and mobility, we determine regions for different combinations of performance (speed) and leakage. Based on these regions, we discuss the trade-off between leakage and delay where the leakage-delay-product is the optimization objective. To assess the accuracy of the proposed model, we compare its predictions with those of HSPICE simulations for both basic digital gates and ISCAS85 benchmark circuits in 45-, 65-, and 90-nm technologies.
Key words: High-performance circuit    Low-leakage circuit    Manufacturing process variation    CMOS integrated circuit
收稿日期: 2011-09-13 出版日期: 2012-06-05
CLC:  TN4  
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Hossein Aghababa
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Ali Afzali-Kusha

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Hossein Aghababa, Behjat Forouzandeh, Ali Afzali-Kusha. High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility. Front. Inform. Technol. Electron. Eng., 2012, 13(6): 460-471.

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http://www.zjujournals.com/xueshu/fitee/CN/10.1631/jzus.C1100273    或    http://www.zjujournals.com/xueshu/fitee/CN/Y2012/V13/I6/460

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