电气工程、计算机技术 |
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基于访问区域特征的高速地址翻译方法 |
王荣华, 孟建熠, 陈志坚, 严晓浪 |
浙江大学 超大规模集成电路设计研究所,浙江 杭州 310027 |
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High speed address translation method based on the memory access region attribute |
WANG Rong-hua, MENG Jian-yi, CHEN Zhi-jian, YAN Xiao-lang |
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China |
引用本文:
王荣华, 孟建熠, 陈志坚, 严晓浪. 基于访问区域特征的高速地址翻译方法[J]. J4, 2014, 48(2): 348-353.
WANG Rong-hua, MENG Jian-yi, CHEN Zhi-jian, YAN Xiao-lang. High speed address translation method based on the memory access region attribute. J4, 2014, 48(2): 348-353.
链接本文:
http://www.zjujournals.com/xueshu/eng/CN/10.3785/j.issn.1008-973X.2014.02.024
或
http://www.zjujournals.com/xueshu/eng/CN/Y2014/V48/I2/348
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[1] ALTMAN E R, EBCIOGLU K, GSCHWIND M, et al. Advances and future challenges in binary translation and optimization [J]. Proceedings of the IEEE, 2001, 89(11): 1710-1722.
[2] CHERNOFF A, HERDEG M, HOOKWAY R, et al. FX!32: A profile-directed binary translator [J]. IEEE Micro, 1998, 18(2): 56-64.
[3] ZHENG C, THOMPSON C. PA-RISC to IA-64: transparent execution, no recompilation [J]. Computer, 2000, 33(3): 47-52.
[4] BELLARD F, QEMU. A fast and portable dynamic translator [C]∥ Proceedings of the annual conference on USENIX Annual Technical Conference. Anaheim, CA:[s. n.], 2005: 4141.
[5] MAGNUSSON P, WERNER B. Efficient memory simulation in SimICS [C]∥ Proceedings of the 28th Annual Simulation Symposium. Phoenix, Arizona: IEEE Computer Society Press, 1995: 62-73.
[6] DEHNERT J C, GRANT B K, BANNING J P, et al., The transmeta code morphing&trade|software: using speculation, recovery, and adaptive retranslation to address real-life challenges [C]∥ Proceedings of the international Symposium on Code Generation and Optimization: Feedback-directed and Runtime Optimization. San Francisco California: \
[s. n.\], 2003: 15-24.
[7] EBCIOGLU K, ALTMAN E R. DAISY: dynamic compilation for 100% architectural compatibility [J]. Sigarch Comput. Archit. News, 1997, 25(2): 26-37.
[8] KONDOH G, KOMATSU H. Dynamic binary translation specialized for embedded systems [C]∥ Proceedings of the 6th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments. Pittsburgh, Pennsylvania: \
[s. n\]. 2010: 157166.
[9] BARAZ L, DEVOR T, ETZION O, et al., IA-32 Execution layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems [C]∥ Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture. San Diego: CAIEEE Computer Society Press, 2003: 191.
[10] C-SKY. 32-bit high performance and low power embedded processor [EB/OL]. [2012-08-01]. http:∥www.c-sky.com. |
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