Please wait a minute...
J4  2013, Vol. 47 Issue (7): 1213-1217    DOI: 10.3785/j.issn.1008-973X.2013.07.012
通信工程、自动化技术     
基于邻行链接访问的低功耗指令高速缓存
项晓燕,陈志坚,孟建熠,严晓浪
浙江大学 超大规模集成电路设计研究所,浙江 杭州 310027    
Low power instruction cache based on adjacent line linking access
XIANG Xiao-yan, CHEN Zhi-jian, MENG Jian-yi, YAN Xiao-lang
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
 全文: PDF 
摘要:

通过分析高速缓存访问的局部性原理,提出当前高速缓存访问行与若干紧邻行链接访问的低功耗指令缓存访问方法.该方法能够在发生相对跳转时依托于相邻行之间的访问链接信息,精确获得跳转目标行的路访问信息,减少对高速缓存标志存储器的访问,达到降低动态功耗的目的.在高速缓存行发生替换时,仅需检测并清除被替换行相邻范围内的若干缓存行的链接信息,从而实现链接关系的正确性.与基于路记忆访问的高速缓存器相比,应用该方法的高速缓存器的动态功耗可以平均减少6%.

关键词: 指令高速缓存低功耗邻行链接访问    
Abstract:

 The behavior of cache accessing was analyzed. A new low power instruction cache accessing method that links the current cache line and its adjacent cache lines was proposed. When a direct jump between cache lines occurs, the adjacent cache line links are reused to get the accurate way information of the target line. Then the accesses of tag array are reduced and tag lookups are avoided to reduce the dynamic power consumption. When a cache line is evicted, only its adjacent cache line links should be checked and invalidated to keep the correctness of the links. Experiment results show that dynamic power consumption can be reduced by 6% on average with the new method compared to the traditional way memorization instruction cache.

Key words:  instruction cache    low power    adjacent cache line linking access
出版日期: 2013-08-15
:  TN 332  
基金资助:

中央高校基本科研业务费资助项目(2012QNA5004).

通讯作者: 陈志坚,男,讲师.     E-mail: chenzj@vlsi.zju.edu.cn
作者简介: 项晓燕(1985-),女,博士生,从事计算机体系结构与高性能嵌入式处理器设计的研究. E-mail: xiangxy@vlsi.zju.edu.cn
服务  
把本文推荐给朋友
加入引用管理器
E-mail Alert
RSS
作者相关文章  

引用本文:

项晓燕,陈志坚,孟建熠,严晓浪. 基于邻行链接访问的低功耗指令高速缓存[J]. J4, 2013, 47(7): 1213-1217.

XIANG Xiao-yan, CHEN Zhi-jian, MENG Jian-yi, YAN Xiao-lang. Low power instruction cache based on adjacent line linking access. J4, 2013, 47(7): 1213-1217.

链接本文:

http://www.zjujournals.com/xueshu/eng/CN/10.3785/j.issn.1008-973X.2013.07.012        http://www.zjujournals.com/xueshu/eng/CN/Y2013/V47/I7/1213

[1] GONZALEZ R, HOROWITZ M. Energy dissipation in general purpose microprocessors [J]. IEEE Journal of Solid-State Circuits, 1996, 31(9):1277-1284.
[2] 孟建熠,严晓浪,葛海通,等.基于指令回收的低功耗循环分支折合技术[J].浙江大学学报:工学版, 2010, 44(4): 632-638.
MENG Jian-yi, YAN Xiao-lang, GE Hai-tong, et al. Instruction recycling based low power branch folding [J]. Journal of Zhejiang University: Engineering Science, 2010,44(4):632-638.
[3] TSAI Y Y, CHEN C H. Energy-efficient trace reuse cache for embedded processors [J]. IEEE Transactions on Very Large Scale Integration Systems, 2011,19(9):1681-1694.
[4] HASEGAWA A, KAWASAKI I, YAMADA K, et al. SH3: high code density, low power [J]. IEEE Micro, 1995, 15(6): 11-19.
[5] INOUE K, ISHIHARA T, MURAKAMI K. Way-predicting set-associative cache for high performance and low energy consumption [C]∥ Proceedings of ISLPED. California: [s.n.], 1999: 273-275.
[6] XU C P, ZHANG G, HAO S Q. Fast way-prediction instruction cache for energy efficiency and high performance [C]∥ Proceedings of NAS. Zhang Jia Jie: [s.n.], 2009: 235-238.
[7] MA A, ZHANG M, ASANOVIC K. Way memorization to reduce fetch energy in instruction caches [C]∥ ISCA Workshop on Complexity Effective Design. Sweden: IEEE, 2001.
[8] XIE Z C, TONG D, CHENG X. WHOLE: a low energy I-cache with separate way history [C]∥ Proceedings of IEEE International Conference on Computer Design. California: IEEE, 2009:137-143.
[9] 龚帅帅,吴晓波,孟建熠,等. 基于历史链接关系的指令高速缓存低功耗方法[J].浙江大学学报:工学版,2011,45(3):467-471.
GONG Shuai-shuai, WU Xiao-bo, MENG Jian-yi, et al. Linking history based low-power instruction cache [J]. Journal of Zhejiang University: Engineering Science, 2011,45(3):467-471.
[10] PANWAR R, RENNELS D. Reducing the frequency of tag compares for low power I:cache design [C]∥ Proceedings of ISLPED. California: [s.n.], 1995:57-62.
[11] C-SKY microsystems. 32-bit high performance and low power embedded processor [EB/OL]. [2003-08-01]. http:∥ www.c-sky.com
[12] BROOKS D, TIWARI V, MARTONOSI M. Wattch: a framework for architectural-level power analysis and optimizations [C]∥ Proceedings of the 27th Annual International Symposium on Computer Architecture. Vancouver: [s.n.], 2000:83-94.

[1] 陈琛, 孙可旭, 冯建宇, 奚剑雄, 何乐年. 超低功耗无片外电容的低压差线性稳压器[J]. 浙江大学学报(工学版), 2017, 51(8): 1669-1675.
[2] 黄正宇, 蒋鑫龙, 刘军发, 陈益强, 谷洋. 基于融合特征的半监督流形约束定位方法[J]. 浙江大学学报(工学版), 2017, 51(4): 655-662.
[3] 周聪聪, 涂春龙, 高云, 王飞翔, 何成, 龚红伟,连平, 叶学松. 腕戴式低功耗无线心率监测装置的研制[J]. 浙江大学学报(工学版), 2015, 49(4): 798-806.
[4] 谭腾飞,马德,黄凯,马琪. 多层图像叠加处理的低功耗自适应流水线设计[J]. 浙江大学学报(工学版), 2015, 49(1): 27-35.
[5] 赵津晨,赵梦恋,吴晓波. 低电源电压超低功耗Delta-Sigma调制器[J]. J4, 2013, 47(7): 1225-1231.
[6] 杭国强, 李锦煊, 王国飞. 新型钟控神经元MOS采样/保持电路[J]. J4, 2012, 46(2): 333-337.
[7] 龚帅帅,吴晓波,孟建熠,丁永林. 基于历史链接关系的指令高速缓存低功耗方法[J]. J4, 2011, 45(3): 467-471.
[8] 徐鸿明,孟建熠,严晓浪,葛海通. 基于高速缓存资源共享的TLB设计方法[J]. J4, 2011, 45(3): 462-466.
[9] 朱丽芳,何乐年,叶益迭. PWM/PSM双模式高压异步整流BUCK电路[J]. J4, 2011, 45(1): 185-190.
[10] 徐扬, 沈继忠. 基于门控时钟的低功耗时序电路设计新方法[J]. J4, 2010, 44(9): 1724-1729.
[11] 孟建熠, 严晓浪, 葛海通. 基于指令回收的低功耗循环分支折合技术[J]. J4, 2010, 44(4): 632-638.
[12] 苑婷,何乐年,柯徐刚. 离线式开关电源控制器芯片的设计与实现[J]. J4, 2010, 44(11): 2130-2136.
[13] 张华锋 卓成 周金芳 陈抗生. 环形行波振荡器电路模型分析与优化设计[J]. , 2009, 43(4): 634-640.
[14] 郭清 马绍宇 黄小伟 韩雁. 低功耗高线性度音频Sigma-Delta调制器[J]. J4, 2009, 43(2): 266-270.
[15] 杭国强, 应时彦. 新型电流型CMOS四值边沿触发器设计[J]. J4, 2009, 43(11): 1970-1974.