Please wait a minute...
浙江大学学报（理学版）
浙江大学学报（理学版）  2016, Vol. 43 Issue (5): 567-572    DOI: 10.3785/j.issn.1008-9497.2016.05.013
电子科学     
基于RTD可编程逻辑门的数字电路3层网络综合算法
姚茂群1, 杨凯1, 许聪源2, 沈继忠2
1. 杭州师范大学 国际服务工程学院, 浙江 杭州 311121;
2. 浙江大学 信息与电子工程学院, 浙江 杭州 310027
Three-layers network synthesis algorithm of digital circuits based on RTD programmable logic gates
YAO Maoqun1, YANG Kai1, XU Congyuan2, SHEN Jizhong2
1. Institute of Service Engineering, Hangzhou Normal University, Hangzhou 311121, China;
2. College of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China
 全文: PDF(969 KB)  
摘要： 随着集成电路的不断发展，CMOS器件的工艺逐渐达到其物理设计极限，研究新器件和新设计方法成为集成电路继续发展的必经之路. 阈值逻辑门因具有强大的逻辑功能而备受关注，共振隧穿二极管（RTD）因其负阻特性在设计阈值逻辑门时更具优势. 由于阈值逻辑门与二进制神经元模型有相似之处，因此可用神经网络模型实现逻辑函数，从而为电路设计提供新的思路. 对基于RTD可编程逻辑门的3层网络算法中的隐层综合算法进行了改进，提出采用汉明距离最大优先覆盖的方法对真向量进行覆盖，从而提高了真向量的覆盖效率，减少了隐层函数个数，并采用真假向量标记的方法简化了隐层综合算法.提出的算法比原隐层综合算法简单，进一步简化了基于RTD可编程逻辑门实现n变量函数的电路.
关键词： 阈值逻辑门;  RTD可编程逻辑门;  综合算法    
Abstract: With the development of integrated circuit, the CMOS technology will face some fundamental physical limittations. The new devices and new design methods thus become very important to the further development of integrated circuit industry. Threshold logic gate has been paid too much attention because of its powerful logic function, and the resonant tunneling diode (RTD) appears to be more suitable for designing the threshold logic gate because of its negative resistance characteristics. As the threshold logic gate and binary neuron model have similar structure, neural network model can be used to implement the logic functions, leading to a new idea for circuit design. In this paper, we improve the hidden layer algorithm of three layers network algorithm based on the RTD programmable logic gate, and propose a method which adopts the biggest distance of Hamming distance in preference to cover the true vector. Our method can improve the coverage efficiency of the true vector, and reduce the number of the hidden layer function. Meanwhile, we use the mark of true vector and false vector to simplify the algorithm. Compared to the original algorithm, the proposed algorithm is concise, and can simplify the circuit of the RTD programmable logic gate to implement the n variable function.
Key words: threshold logic gate    RTD programmable logic gate    synthesis algorithm
收稿日期: 2015-04-07 出版日期: 2016-05-01
CLC:  TN47  
基金资助: 国家自然科学基金资助项目（61271124，61471314）；浙江省自然科学基金资助项目（LY15F010011）.
作者简介: 姚茂群(1967-),ORCID:http://orcid.org/0000-0001-6484-4972,女,博士,教授,主要从事数字集成电路与系统、嵌入式系统与应用研究,E-mail:yaomaoqun@163.com.
服务　　
把本文推荐给朋友
加入引用管理器
E-mail Alert
RSS
作者相关文章　　
姚茂群
杨凯
许聪源
沈继忠

引用本文:

姚茂群, 杨凯, 许聪源, 沈继忠. 基于RTD可编程逻辑门的数字电路3层网络综合算法[J]. 浙江大学学报（理学版）, 2016, 43(5): 567-572.

YAO Maoqun, YANG Kai, XU Congyuan, SHEN Jizhong. Three-layers network synthesis algorithm of digital circuits based on RTD programmable logic gates. Journal of ZheJIang University(Science Edition), 2016, 43(5): 567-572.

链接本文:

https://www.zjujournals.com/sci/CN/10.3785/j.issn.1008-9497.2016.05.013    或    https://www.zjujournals.com/sci/CN/Y2016/V43/I5/567

[1] IWAI H. Materials and structures for future nano CMOS[C]//Proceeding of Nanotechnology Materials and Devices Conference. Jeju: IEEE Press,2011:14-18.
[2] HARIHARAN A N, PONTARELLI S, OTTAVI M, et al. Modeling open defects in nanometric scale CMOS[C]//Proceeding of Defect and Fault Tolerance in VLSI Systems. Kyoto: IEEE Press,2010:249-257.
[3] [ZK(#]MURAMATSU N, OKAZAKI H, WAHO T. A novel oscillation circuit using a resonate-tunneling diode[C]//Proceeding of Circuits and Systems. Kobe:IEEE Press, 2005:2341-2344.
[4] [JP2]ZHENG Yexin, HUANG Chao. Complete logic functionality of reconfigurable RTD circuit elements[J]. IEEE Transactions on Nanotechnology,2009,8(5):631-642.[JP]
[5] 韦一,沈继忠.基于阈值逻辑的逻辑函数综合算法研究[J].电子与信息学报,2011,33(7):1775-1778. WEI Yi, SHEN Jizhong. Research of logic function synthesis algorithm based on threshold logic[J]. Journal of Electronics & Information Technology,2011,33(7):1775-1778.
[6] [JP2]MIRHOSEINI S M, SHARIFI M J, BAHREPOUR D. New RTD-based general threshold gate topologies and application to three-input XOR logic gates[J]. Journal of Electrical and Computer Engineering,2010,35(1):1-4.[JP]
[7] 杭国强,李锦煊,王国飞.新型钟控神经元MOS采样/保持电路[J].浙江大学学报:工学版,2012,46(2):333-337. HANG Guoqiang, LI Jinxuan, WANG Guofei. A novel sample and hold circuit using clocked neuron-MOS scheme[J].Journal of Zhejiang University:Engineering Science,2012,46(2):333-337.
[8] WANG D, CHAUDHARI N S. An approach for construction of Boolean neural networks based on geometrical expansion[J]. Neurocomputing,2004,57:455-461.
[9] ZHANG Hao, WANG Xingyuan, LIN Xiaohui. Synchronization of boolean networks with different update schemes[J]. IEEE/ACM Transactions on Computational Biology and Bioinformatics,2014,11(5):965-972.
[10] 韦一.基于RTD的通用逻辑单元设计及其应用[D].杭州:浙江大学,2011:48-59. WEI Yi. General Logic Units Design Based on RTD and Its Application[D].Hangzhou:Zhejiang University,2011:48-59.
[11] QUINTANA J M, AVEDILLO M J, PETTENGHI H. Programmable logic gate based on resonant tunneling devices[C]//IEEE International Symposium on Circuits and Systems. Vancouver:IEEE Press, 2004:697-700.
[12] [JP3]CHEN K, AKEYOSHI, MAEZAWA K. Monolithic integration of resonant tunneling diodes and FET's for monostable-bistable transition logic elements (MOBILE's) [J]. Electron Device Letters,1995,16(2):70-73.[JP]
[13] GRAY D L, MICHEL A N. A training algorithm for binary feed forward neural networks[J]. IEEE Transactions on Neural Networks,1992,3(2):176-194.
[14] KIM J H, PARK S K. The geometrical learning of binary neural networks[J]. IEEE Transactions on Neural Networks,1995,6(1):237-247.
[1] 姚茂群,冯杰,刘志强,李聪辉. 基于RTD可编程逻辑门的n变量函数实现算法[J]. 浙江大学学报（理学版）, 2022, 49(4): 474-480.
[2] 姚茂群, 周传鑫, 李聪辉. 基于和图的电流型CMOS三变量通用逻辑门设计[J]. 浙江大学学报（理学版）, 2021, 48(5): 565-572.
[3] 姚茂群, 冯杰, 王竹萍. 基于RTD的三变量特征阈值逻辑门及通用阈值逻辑门设计[J]. 浙江大学学报（理学版）, 2020, 47(1): 86-94.
[4] 应时彦, 孔伟名, 肖林荣, 王伦耀. 基于互补型SET的通用阈值逻辑门设计[J]. 浙江大学学报（理学版）, 2017, 44(4): 424-428.