电子科学 |
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基于和图的电流型CMOS三变量通用逻辑门设计 |
姚茂群, 周传鑫, 李聪辉 |
杭州师范大学 信息科学与技术学院,浙江 杭州 311121 |
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Design of current-mode CMOS three-variable universal logic gates based on HE map |
YAO Maoqun, ZHOU Chuanxin, LI Conghui |
School of Information Science and Technology, Hangzhou Normal University, Hangzhou 311121, China |
1 PANDEY N,GUPTA K,BHATIA G,et al. MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells[J]. Microelectronics Journal,2016,57(C):13-20. doi:10.1016/j.mejo.2016.08.016 2 GHOSH A,JAIN A,SINGH N B,et al. Single electron threshold logic based Feynman gate implementation[C]// International Conference on Research in Computational Intelligence & Communication Networks. Kolkata:IEEE,2017:266-268. 3 MAAN A K,JAYADEVI D A,JAMES A P. Supplementary material:A survey of memristive threshold logic circuits[J]. IEEE Transactions on Neural Networks & Learning Systems,2017,28(8):1734-1746. DOI:10.1109/TNNLS.2016.2547842 4 FAN D. Ultra-low energy reconfigurable spintronic threshold logic gate[C]// Proceedings of the 26th Edition on Great Lakes Symposium on VLSI. Boston:IEEE,2016:385-388. DOI:10.1145/2902961. 290 2994 5 DARA C B,HANIOTAKIS T,TRAGOUDAS S. Delay analysis for current mode threshold logic gate designs[J]. IEEE Transactions on Very Large Scale Integration Systems,2017(99):1-9. doi:10.1109/tvlsi.2016.2608953 6 MAAN A K,JAMES A P. Voltage controlled memristor threshold logic gates[C]// 2016 IEEE Asia Pacific Conference on Circuits and Systems. Jeju:IEEE,2016,376-379. DOI:10.1109/APCCAS. 2016.7803980 7 潘张鑫,马汝星,陈偕雄. 三变量通用阈值逻辑门的设计[J]. 浙江大学学报(理学版),2005,32(1):42-44. DOI:10.3785/j.issn.1008-9497.2005.01.011 PAN Z X,MA R X,CHEN X X. Design of three-variable universal-threshold-logic gates[J]. Journal of Zhejiang University (Science Edition),2005,32(1):42-44. DOI:10.3785/j.issn.1008-9497.2005. 01.011 8 WU X,DENG X,YING S. Design of ternary current-mode CMOS circuits based on switch-signal theory[J]. Journal of Electronics,1993,10(3):193-202. DOI:10.1007/bf02684547 9 TEMEL T,MORGUL A. Implementation of multi-valued logic gates using full current-mode CMOS circuits[J]. Analog Integrated Circuits & Signal Processing,2004,39(2):191-204. DOI:10.1023/b:alog.0000024066.66847.89 10 张官志,姚茂群,施锦河. 和图及其在I2L电路设计中的应用[J]. 电路与系统学报,2011,16(6):94-98. doi:10.3969/j.issn.1007-0249.2011.06.017 ZHANG G Z,YAO M Q,SHI J H. HE map and its application in the design of I2L circuits[J]. Journal of Circuits and Systems,2011,16(6):94-98. doi:10.3969/j.issn.1007-0249.2011.06.017 11 姚茂群,张官志,施锦河. 阈算术代数系统及多值电流 型CMOS电路设计[J]. 电子与信息学报,2012,34(7): 1773-1778. DOI:10.3724/SP.J.1146.2011. 01185 YAO M Q,ZHANG G Z,SHI J H. Threshold-arithmetic algebraic system and design of multiple-valued CMOS circuits[J]. Journal of Electronics & Information Technology,2012,34(7):1773-1778. DOI:10.3724/SP.J.1146.2011.01185 12 陈偕雄,沈继忠. 近代数字理论[M].杭州:浙江大学出版社,2001. DOI:10.1515/9783110506129 CHEN X X,SHEN J Z. Modern Digital Theory[M]. Hangzhou:Zhejiang University Press,2001. DOI:10.1515/9783110506129 13 姚茂群,沈继忠. 基于谱技术的电流型CMOS电路设计[J]. 杭州电子工业学院学报,2000(6):73-77. YAO M Q,SHEN J Z. Design of current-mode cmos circuits based on spectral techniques[J]. Journal of Hangzhou Institute of Electronic Engineering,2000(6): 73-77. 14 LU S L,ERCEGOVAC M. A novel CMOS implementation of double-edge-triggered flip-flops[J]. IEEE Journal of Solid-State Circuits,1990,25(4):1008-1010. DOI:10.1109/4.58294 |
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