A 2-tap analog-adaptive decision feedback equalizer (DFE) was designed using 0.18 μm CMOS technology for high-speed backplane communication. Half-rate architecture was adopted to improve the speed and reduce the power. And analog least-mean-square adaptive circuit composed of multiplier and integrator was designed. In order to improve the effect of adaptive algorithm, LMS analog circuit was optimized, which not only ensured the requirement of the adaptive convergence and stability, but also obtained the smaller integral error to output the stable bias voltage for integrator. The whole chip area including pads was 0.378 mm2. The test results show that DFE can compensate 12 dB channel loss at 4 GHz when adaptive circuit was turned on, and the vertical opening and horizontal opening reached 275.5 mV and 72 ps, respectively, which was significantly better than that when it was turned off. The power consumption was 49.9 mW at the supply voltage of 1.8 V and the rate of 8 Gb/s. The designed analog-adaptive DFE circuit is more suitable for high-speed communication link systems of 25 G and above.
Fig.9Convergence characteristics of LMS algorithm under different integral time constants
Fig.10Simulation results of adaptive equalization effects
Fig.11Chip micrograph
Fig.12Chip measurement scheme and instruments
Fig.13Measurement results for 8 Gb/s 2-tap analog-adaptive DFE
来源
CMOS工艺
v/(Gb·s-1)
结构
DFE自适应
S/mm2
P/mW
L/dB
U/V
注：1)包含时钟及数据恢复(clock and data recovery, CDR)的功耗
本文
0.18 μm
8.00
半速率DFE
模拟
0.378
49.9
12.0
1.8
文献[14]
0.18 μm
6.25
半速率DFE
数字
0.33
49.5
9.7
1.8
文献[15]
40 nm
15.00
CTLE+半速率预处理DFE
模拟
2.03
72.5
23.0
1.1
文献[16]
0.13 μm
10.00
FFE+全速率DFE
模拟
5.52
452.01)
16.3
1.2
Tab.1Performance comparison among different adaption equalizers
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