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J4  2013, Vol. 47 Issue (5): 837-842    DOI: 10.3785/j.issn.1008-973X.2013.05.015
    
Design and application of test structure array based on modular unit
ZHANG Bo, PAN Wei-wei, YE Yi, ZHENG Yong-jun, SHI Zheng, YAN Xiao-lang
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China)
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Abstract  

A modular unit based design method of scalable test structure array is presented, aiming to increasing mask utilization ratio of test chips in nanometer scale IC manufacturing. Implemented in 45 nm CMOS technology, two large-scale test structure arrays, with 32×32 and 64×64 units respectively, had been designed and fabricated as the experiments. By combining the device-under-test (DUT) and the transmission gates into one standard modular unit, the area utilization reached 79.31% and 70.8% for these experiments. Process defects such as via-induced metal loss were reported after testing data analysis. The results demonstrated that the process window could be sufficiently tracked with those arrays, which further proves the accuracy and effectiveness of the presented design method.



Published: 01 May 2013
CLC:  TN 43  
Cite this article:

ZHANG Bo, PAN Wei-wei, YE Yi, ZHENG Yong-jun, SHI Zheng, YAN Xiao-lang. Design and application of test structure array based on modular unit. J4, 2013, 47(5): 837-842.

URL:

http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2013.05.015     OR     http://www.zjujournals.com/eng/Y2013/V47/I5/837


基于模块化单元的测试结构阵列设计及其应用

针对纳米级半导体制造工艺中传统测试芯片掩模面积利用率低的问题,提出一种基于模块化单元的可扩展成品率测试结构阵列设计方法. 基于45 nm CMOS制造工艺分别实现32×32和64×64  2个大规模的测试结构阵列, 模块化单元的有效面积利用率达7931%和708%|流片后通过测试数据的分析能够发现通孔缺失、通孔尺寸变大以及大尺寸缺陷导致金属缺失等工艺缺陷问题.试验结果同时表明,该方法将传输门器件和测试结构组合成模块化单元; 不仅能够实现对测试结构的四端测量, 保证测试结果的正确性, 并且能够减小成品率测试芯片的掩模面积.

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