[1] WU Ling-juan, LU Wei-jun, YU Dun-shan. Research of weak signal acquisition algorithms for high sensitivity GPS receivers [C]∥ Conference on PrimeAsia. Shanghai: IEEE, 2009: 173-176.
[2] SOKOLOVA N, BORIO D, FORSSELL B, et al. Doppler rate measurements in standard and high sensitivity GPS receivers: theoretical analysis and comparison [C]∥ Conference on IPIN. Hoenggerberg: IEEE, 2010: 19.
[3] SCHON S, BIELENBERG O. On the capability of high sensitivity GPS for precise indoor positioning [C]∥ 5th Workshop on Positioning, Navigation and Communication. Hannover: IEEE, 2008: 121-127.
[4] 张朝杰, 金小军, 杨伟君,等. 高灵敏度微小卫星可变带宽接收机设计[J]. 浙江大学学报:工学版, 2011, 45(4): 588-590.
ZHANG Chao-jie, JIN Xiao-jun, YANG Weijun, et al. Design of variable loop bandwidth high sensitivity micro-satellite receiver [J]. Journal of Zhejiang University: Engineering Science, 2011, 45(4): 588-590.
[5] SERNA E P, THOMBRE S, VALKAMA M, et al. Local oscillator phase noise effects on GNSS code tracking [J]. Inside GNSS, 2010, 5(6): 52-62.
[6] RAZAVI B. RF microelectronics [M]. America: Pearson Education, 1998: 33.
[7] HEGAZI E, SJLAND H, ABIDI A A. A filtering technique to lower LC oscillator phase noise [J]. IEEE Journal of SolidState Circuits, 2001, 36(12): 1921-1930.
[8] LEVANTINO S, ROMANO L, PELLERANO S, et al. Phase noise in digital frequency dividers [J]. IEEE Journal of SolidState Circuits, 2004, 39(5): 775-784.
[9] VAUCHER C S, FERENCIC I, LOCHER M, et al. A family of lowpower truly modular programmable dividers in standard 0.35-μm CMOS technology [J]. IEEE Journal of Solid-State Circuits, 2000, 35(7): 1039-1045.
[10] RHEE W. Design of high-performance CMOS charge pumps in phaselocked loops [C]∥ IEEE Proceedings of ISCAS. Orlando: IEEE, 1999, 2(7): 545-548.
[11] GUPTA M, SONG B S. A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration [J]. IEEE Journal of Solid-State Circuits, 2006, 41(12): 2842-2851.
[12] GRAMEGNA G, MATTOS P G, LOSI M, et al. A 56 mW 23-mm2 single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1mm2 radio [J]. IEEE Journal of SolidState Circuits, 2006, 41(3): 540-551.
[13] WOO K, LIU Yong, NAM E, et al. Fast-lock hybrid PLL combining fractional-N and integer-N modes of differing bandwidths [J]. IEEE Journal of Solid-State Circuits, 2008, 43(2): 379-389.
[14] WU Ting, HANUMOLU P K, MAYARAM K, et al. Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers [J]. IEEE Journal of Solid-State Circuits, 2009, 44(2): 427-435. |