Design methodology of FPGA based reconfigurable video encoder
DU Juan, DING Dan-dan, YU Lu
Institute of Information and Communication Engineering, Zhejiang University,
Zhejiang Provincial Key Laboratory of Information Network Technology, Hangzhou 310027, China
Field programmable gate array (FPGA) based reconfigurable video encoder was presented in this paper. In order to enhance the system throughout and facilitate Function unit (FU) reusability and extensibility, a hierarchical FU partition method with multiple granularities is proposed. For simplicity in reconfiguration and complexity reduction, we adopt different storage structure as the way of connecting data. Based on the proposed methods, an efficient architecture for I-frame video encoder supporting H.264/AVC and AVS was realized. As a result, the proposed architecture can be easily reconfigured to satisfy 25 (37) frames per second encoding of 1 080p HD video of H.264/AVC (AVS) at the working frequency of 186MHz in Xilinx Virtex5 FPGA, and reduce 33% area cost when compared with two separate designs．
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