[1] SINGH H, GILL S S. Approaches to channel equalization [C]∥ Advanced Computing and Communication Technologies (ACCT). Panipat : [s. n.], 2012: 172-175.
[2] SONG San-quan, STOJANOVIC V. A 6.25 Gb/s voltage-time conversion based fractionally spaced linear receive equalizer for mesochronous high-speed links [J]. Solid-State Circuits, 2011, 46(5): 1183-1197.
[3] LEE H, CHANG K Y K, CHUN J H, et al. A 16 Gb/s link, 64 GB/s bidirectional asymmetric memory interface [J]. Solid-State Circuits, 2009, 44(4):1235-1247.
[4] BALAMURUGAN G, CASPER B, JAUSSI J E, et al. Modeling and analysis of high-speed I/O links [J]. Advanced Packaging, 2009, 32( 2): 237-247.
[5] ANALUI B, BUCKWALTER J F, HAJIMIRI A. Data-dependent jitter in serial communications [J]. Microwave Theory and Techniques, 2005, 53(11):3388-3397.
[6] LIU C, CAROSELLI J. Comparison of signaling and equalization schemes in high speed SerDes (10-25 Gb/s) [C]∥ DesignCon. Santa: [s. n.], 2007.
[7] CAROSELLI J, LIU C. An analytic system model for high speed interconnects and its application to the specification of signaling and equalization architectures for 10Gbps backplane communication [C]∥DesignCon.Santa Clara: [s. n.], 2006.
[8] YAO Wei, SHI Yi-yu, HE Lei, et al. Worst-case estimation for data-dependent timing jitter and amplitude noise in high-speed differential link [J]. Very Large Scale Integration (VLSI) Systems, 2012, 20(1):89-97.
[9] 钟华,郑林华,金国平.基于最大比特速率准则的FMT频域均衡算法[J].电子与信息学报,2010, 32(6): 1429-1434.
ZHONG Hua, ZHENG Lin-hua, JIN Guo-ping. Bit-rate maximization frequency-domain equalization algorithm for FMT systems [J]. Journal of Electronics and Information Technology, 2010, 32(6): 1429-1434.
[10] BAJPAI A, LAKSHMANAN M K, NIKOOKAR H. Channel equalization in wavelet packet modulation by minimization of peak distortion [C]∥ Personal Indoor and Mobile Radio Communications (PIMRC) . Toronto: IEEE, 2011:152-156.
[11] REN Ji-hong, KYUNG S O. Multiple edge responses for fast and accurate system simulations [J]. IEEE Transactions on Advanced Packaging, 2008, 31(4):741-748.
[12] STOJANOVIC V, HOROWITZ M. Modeling and analysis of high-speed links [C]∥ IEEE Custom Integrated Circuits Conference. San Jose: IEEE, 2003: 589-594.
[13] ZAMEK I, ZAMEK S. Definitions of jitter measurements terms and relationships [C]∥ International Test Conference. Austin: IEEE, 2005:1-10.
[14] CHANG Yu, DAN O, CHIRS M. Jitter modeling in statistical link simulation [C]∥ IEEE International Symp on Electromagnetic Compatibility. Detroit: IEEE, 2008: 1-4.
[15] CHANG Yu, DAN O. System-level modeling and simulation of periodic jitter in high-speed links [C]∥ Electrical Performance of Electronic Packaging and Systems (EPEPS). Austin: IEEE, 2010: 117-120.
[16] KYUNG S O, LAMBRECHT F, CHANG S. Accurate system voltage and timing margin simulation in high-speed I/O system designs [J]. IEEE Transactions on Advanced Packaging, 2008, 31(4): 722-730. |