According to feedback decomposition theorem (FDT), the gate-drain capacitance of a transistor was decomposed into the input and output nodes. Then the influence of gate-drain capacitance on input impedance and noise figure of low noise amplifier (LNA) were discussed. Based on the analytic result, revised input matching and noise figure formulas were developed, also the noise optimization method under the constraint of power dissipation was proposed. The post-layout simulation results show that the 2.4 GHz LNA, based on SMIC 0.18 μm RF CMOS(Complementary Metal Oxide Semiconductor) technology, consumes a low DC power of 2.4 mW from a 1.2 V supply, noise figure of 1.0 dB, power gain of 16.3dB, input and output losses below -22 dB, and input third-order intercept point of -3.2 dBm.Compared with existing designs, the proposed 2.4 GHz LNA based on the revised formulas had lower power dissipation, better input impedance matching and lower noise factor．
［1］ SHAEFFER D K, LEE T H. A 1.5- V, 1.5- GHz CMOS low noise amplifier［J］. IEEE Journal of Solid- State Circuits, 1997, 32(5):745-759．
［2］ BELOSTOTSKI L, HASLE J W. Noise figure optimization of inductively degenerated CMOS LNAs with integrated gate inductors ［J］. IEEE Transactions on Circuits and Systems I, 2006, 53(7):1409-1422．
［3］ NGUYEN T K, KIM C K, IHM G J, et al. CMOS low noise amplifier design optimization techniques［J］. IEEE Transactions on Microwave Theory and Techniques, 2004, 52(5):1433-1442．
［4］ ANDREANI P, SJOLAND H. Noise optimization of an inductively degenerated CMOS low noise amplifier［J］. IEEE Transactions on Circuits and Systems.II, 2001, 48(9):835-841.
［5］ ENZ C. An MOS transistor model for RF IC design valid in all regions of operation［J］. IEEE Transactions on Microwave Theory and Techniques, 2002, 50(1):342-348．
［6］ WEISS G. Comment on a theorem dual to Millers theorem［J］. IEEE Transactions on Education, 1999,42(4):349-351．
［7］ POTIRAKIS S M, ALEXAKIS G E. The feedback decomposition theorem: the evolution of Millers theorem［J］. International Journal of Electron Engineering Education, 1998, 85(5):571-587．
［8］ HAKCHUL J, HEESAUK J, ICKHYUN S, et al. Design optimization of a 10 GHz low noise amplifier with gate drain capacitance consideration in 65 nm CMOS technology［C］ ∥Solid State and Integrated Circuit Technology, 2008. 9th International Conference. Beijing:IEEE,2008:1480-1483．
［9］ BELOSTOTSKI L, HASLE J W. Noise figure optimization of WideBand InductivelyDegenerated CMOS LNAs［C］∥ Circuits and Systems, 2007. MWSCAS 200750th Midwest. Montreal:IEEE,2007:1002-1005．
［10］ KIM HS, LI XP, ISMAIL M. A 24GHz CMOS low noise amplifier using an inter stage matching inductor［C］∥The 42nd Midwest Symposium on Circuits and Systems. New Mexico:IEEE,1999:1040-1043．
［11］ YANG Tao. Design of A 24 GHz low noise amplifier in 025um CMOS technology［C］∥IEEE 2007 International Symposium on Microwave. Honolulu:IEEE,2007:392-395．
［12］ YANG Xiaoming, THOMAS W, MAMACKEN J. Design of LNA at 24 GHz using 025um technology［C］∥Silicon Monolithic Integrated Circuits in RF Systems, 2001. Michigan:IEEE,2001:12-17．
［13］ CHENG Kuohua, CHU Hsin, JOU C F. A novel 2.4 GHz LNA with digital gain control using 0.18 μm CMOS［C］∥ Microwave Conference Proceedings,2005. AsiaPacific: IEEE,2005: 4-7.
