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浙江大学学报(工学版)
计算机技术﹑电信技术     
多晶硅栅对LDMOS-SCR器件ESD防护性能的影响
黄龙1, 梁海莲1, 顾晓峰1, 董树荣2, 毕秀文1, 魏志芬3
1.江南大学 轻工过程先进控制教育部重点实验室,江苏 无锡 214122;2.浙江大学 微电子与光电子研究所,浙江 杭州 310027;3.西安西电电力系统有限公司,陕西 西安 710077
Effect of poly-silicon gate on ESD protection performance of LDMOS-SCR devices
HUANG Long1, LIANG Hai-lian1, GU Xiao-feng1, DONG Shu-rong2, BI Xiu-wen1, WEI Zhi-fen3
1. Key Laboratory of Advanced Process Control for Light Industry, Ministry of Education, Jiangnan University, Wuxi 214122, China; 2. Institute of Microelectronics and Optoelectronics, Zhejiang University, Hangzhou 310027, China; 3. Xi’an XD Power Systems Co., Ltd., Xi’an 710077, China
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摘要:

为了研究多晶硅栅对内嵌可控硅(SCR)的横向扩散金属氧化物半导体(LDMOS-SCR)器件静电放电(ESD)防护性能的影响,基于0.35 μm Bipolar-CMOS-DMOS (BCD)工艺制备了LDMOS-SCR与SCR器件,并利用传输线脉冲测试比较它们的ESD特性.通过仿真2种器件在不同强度ESD应力下的电流密度分布,比较器件内部触发电流泄放路径的开启顺序;通过仿真2种器件在强电压回滞下的电流线和晶格温度的分布,分析因电场影响电流泄放的方式以及温度的分布而导致ESD鲁棒性的差异.仿真和测试结果表明,与SCR相比,具有多晶硅栅的LDMOS-SCR有多条导通路径且开启速度快,有更均匀的电流和电场分布;触发电压降低了12.5%,失效电流提高了27.0%,ESD鲁棒性强.

Abstract:

To study the effect of poly-silicon gate on the electrostatic discharge (ESD) protection performance of laterally diffusion metal-oxide-semiconductor (LDMOS) devices with embedded silicon controlled rectifier (SCR), we prepared SCR and LDMOS-SCR devices in a 0.35 μm Bipolar-CMOS-DMOS (BCD) process and measured their ESD characteristics by using transmission line pulse test system. We compared their turn-on sequence of trigger current discharge paths by simulated internal current density distribution at different ESD pulse. By simulating their current line and lattice temperature distributions in the turn-on state, we also compared their ESD robustness resulting from the different electric field induced current discharge methods and the temperature distribution. Both simulation and test results show that, compared with SCR, the LDMOS-SCR with poly-silicon gate has more conduction paths and more uniform current and electric field distributions, turns on faster, has a trigger voltage decreased by 12.5% and a failure current increased by 27.0%, and exhibits the stronger ESD robustness.

出版日期: 2015-02-01
:  TN 386.1  
基金资助:

国家自然科学基金资助项目(61171038,61150110485);中央高校基本科研业务费专项资金(JUSRP51323B, JUDCF13032);江苏省科技厅产学研联合创新资金前瞻性联合研究项目(BY2013015-19);江苏省普通高校研究生创新计划CXLX13_747)

通讯作者: 顾晓峰,男,教授、博导     E-mail: xgu@jiangnan.edu.cn
作者简介: 黄龙(1988—),男,硕士生,主要从事集成电路可靠性研究.E-mail: 124252911@qq.com
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引用本文:

黄龙, 梁海莲, 顾晓峰, 董树荣, 毕秀文, 魏志芬. 多晶硅栅对LDMOS-SCR器件ESD防护性能的影响[J]. 浙江大学学报(工学版), 10.3785/j.issn.1008-973X.2015.02.025.

HUANG Long, LIANG Hai-lian, GU Xiao-feng, DONG Shu-rong, BI Xiu-wen, WEI Zhi-fen. Effect of poly-silicon gate on ESD protection performance of LDMOS-SCR devices. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 10.3785/j.issn.1008-973X.2015.02.025.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2015.02.025        http://www.zjujournals.com/eng/CN/Y2015/V49/I2/366

[1] HUANG C Y, CHIU F C, CHEN Q K, et al. An SCR-Incorporated BJT device for robust ESD protection withhigh latch up immunity in high-voltage technology [J]. IEEE Transactions on Device and Materials Reliability, 2012, 12(1): 113-123.
[2] SHRIVASTAVA M, GOSSNER H. A review on the ESD robustness of drain extended MOS devices [J]. IEEE Transctions on Device and Materials Reliability, 2012, 12(4): 615-624.
[3] 李梅芝,陈星弼.栅压对LDMOS在瞬态大电流下工作的温度影响[J].半导体学报, 2008, 28(8): 1256-1260.
LI Mei-zhi, CHEN Xing-bi. Influence of gate voltage on temperature of LDMOS under ultra-high transient currents [J]. Chinese Journal of Semiconductors, 2008, 28(8): 1256-1260.
[4] 朱科翰,董树荣,韩雁,等.不同栅压下NMOS器件的静电防护性能[J].浙江大学学报:工学版,2010, 44(1): 142-144.
ZHU Ke-han, DONG Shu-rong, HAN Yan, et al. ESD protection of NMOS device at different gate bias [J]. Journal of Zhejiang University: Engineering Science, 2010, 44(1): 142-144.
[5] LIU Z W, Liou J J, DONG S R, et al. Silicon-controlled rectifier stacking structure for high-voltage ESD protection applications [J]. IEEE Electron Devices Letters, 2010, 31(8): 845-847.
[6] KER M D, LIN K H. The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latch up-free power-rail ESD clamp circuit for LCD driver Ics [J]. IEEE Journal of Solid-State Circuits, 2005, 40(8): 1751-1759.
[7] MA F, ZHANG B, HAN Y, et al. High holding voltage SCR-LDMOS stacking structure with ring-resistance-triggered technique [J]. IEEE Electron Device Letters, 2013, 34(9): 1178-1180.
[8] CHANG W J, KER M D. The impact of drift implant and layout parameters on ESD robustness for on-chip ESD protection devices in 40-V CMOS technology [J]. IEEE Transactions on Device and Materials Reliability, 2007, 7(2): 324-332.
[9] JIANG L L, FAN H, HE C, et al. A reduced surface current LDMOS with stronger ESD robustness [C]∥ 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology. Xi’an: IEEE, 2012: 13.

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