电子、通信与自动控制技术 |
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H.264/AVC子像素插值的高性能流水线设计及实现 |
李春澍1,黄凯1,修思文1,马德1,葛海通2,严晓浪1 |
1. 浙江大学 超大规模集成电路设计研究所,浙江 杭州 310027; 2. 杭州中天微系统有限公司,浙江 杭州 310027 |
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High efficient pipeline design and implementation for sub-pixel interpolation process in H.264/AVC |
LI Chun-shu1, HUANG Kai1, XIU Si-wen1, MA De1, GE Hai-tong2, YAN Xiao-lang1 |
1.Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; 2.Hangzhou csky Microsystem Corporation, Hangzhou 310027, China |
引用本文:
李春澍,黄凯,修思文,马德,葛海通,严晓浪. H.264/AVC子像素插值的高性能流水线设计及实现[J]. J4, 2011, 45(7): 1187-1193.
LI Chun-shu, HUANG Kai, XIU Si-wen, MA De, GE Hai-tong, YAN Xiao-lang. High efficient pipeline design and implementation for sub-pixel interpolation process in H.264/AVC. J4, 2011, 45(7): 1187-1193.
链接本文:
https://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2011.07.008
或
https://www.zjujournals.com/eng/CN/Y2011/V45/I7/1187
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[1] ITUT Rec. H.264 and ISO/IEC 1448610 AVC. Draft ITUT recommendation and final draft international standard of joint video specification [S]. [S. l.]: JVT, 2003. [2] LIN Chienchang, CHEN Jiawei, CHANG Hsiucheng, et al. A 160K gates/45 kB SRAM H.264 video decoder for HDTV applications [J]. IEEE Journal of SolidState Circuits, 2007, 42(1): 170-182. [3] XU Ke, CHOY Chiusing. A powerefficient and selfadaptive prediction engine for H.264/AVC decoding [J]. IEEE Transactions on Very Large Scale Integration Systems, 2008, 16(3): 302-313. [4] LEI Yu, LI Hui, HUANG Kai, et al. A H.264 video decoder with scheme of efficient bandwidth optimization for motion compensation [C]∥ International Symposium on Communications and Information Technologies. Sydney, Australia: IEEE, 2007: 531-534. [5] YANG Kun, ZHANG Chun, DU Guoze, et al. A hardwaresoftware codesign for H.264/AVC decoder [C]∥ Asia SolidState Circuit Conference. Hangzhou, China: IEEE, 2006: 119-122. [6] 戴郁,李冬晓,郑伟,等. H.264/AVC运动补偿的高效插值结构设计[J]. 浙江大学学报:工学版, 2009, 43(2): 255-260. DAI Yu, LI Dongxiao, ZHENG Wei, et al. Efficient interpolation architecture design for motion compensation in H.264/AVC [J]. Journal of Zhejiang University: Engineering Science, 2009, 43(2): 255-260. [7] WANG Ronggang, LI Mo, LI Jintao, et al. High throughput and low memory access subpixel interpolation architecture for H.264/AVC HDTV decoder [J]. IEEE Transactions on Consumer Electronics, 2005, 51(3): 1006-1013. [8] CHUANG Tzuder, CHANG Lomei, CHIU Tsaiwei, et al. Bandwidthefficient cachebased motion compensation architecture with dramfriendly data access control [C]∥ Acoustics, Speech and Signal Processing. Taipei, Taiwan, China: IEEE, 2009: 2009-2012. [9] 姚栋,虞露. MPEG4运动补偿的亚像素内插过程及其硬件实现[J]. 浙江大学学报:工学版, 2005, 39(11): 1703-1707. YAO Dong, YU Lu. Subpixel interpolation of MPEG4 motion compensation and its hardware implementation [J]. Journal of Zhejiang University: Engineering Science, 2005, 39(11): 1703-1707. [10] KIM J H, HYUN G H, LEE H J. Cache organization for H.264/AVC motion compensation [C]∥ Embedded and RealTime Computing Systems and Applications. Daegu, Korea: IEEE, 2007: 534-541. [11] FINCHELSTEIN D F, SZE V, CHANDRAKASAN A P. Multicore processing and efficient onchip caching for H.264 and future video decoders [J]. IEEE Transactions on Circuits and Systems for Video Technology, 2009, 19(11): 1704-1722. |
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