10.1631/FITEE.14e0087," /> 10.1631/FITEE.14e0087,"/> 10.1631/FITEE.14e0087,"/> 基于65 nm CMOS工艺且应用于60 GHz接收机的折叠下变频混频器
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Front. Inform. Technol. Electron. Eng.  2014, Vol. 15 Issue (12): 1190-1199    DOI: 10.1631/jzus.C1400087
    
Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology
Najam Muhammad Amin, Zhi-gong Wang, Zhi-qun Li
Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
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Abstract  We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator (LO) frequency of 12 GHz, which down-converts the RF band to an intermediate frequency (IF) band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power (LP) CMOS process with an active chip area of only 0.0179 mm2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain (VCG) of 9.8 dB, a double sideband noise figure (DSB-NF) of 11.6 dB, and a linearity in terms of input 1 dB compression point (Pin,1dB) of 鈭?3 dBm are measured. The mixer draws a current of 5 mA from a 1.2 V supply dissipating a power of only 6 mW.

Key words： Folded mixer      Current reuse      Low power      Inductorless design      Direct conversion

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Received: 13 March 2014      Published: 05 December 2014
CLC:  TN4  
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Najam Muhammad Amin
Zhi-gong Wang
Zhi-qun Li
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Najam Muhammad Amin, Zhi-gong Wang, Zhi-qun Li. Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology. Front. Inform. Technol. Electron. Eng., 2014, 15(12): 1190-1199.

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http://www.zjujournals.com/xueshu/fitee/10.1631/jzus.C1400087     OR     http://www.zjujournals.com/xueshu/fitee/Y2014/V15/I12/1190


基于65 nm CMOS工艺且应用于60 GHz接收机的折叠下变频混频器

此文提出了一个折叠下混频电路。此混频器应用在一个60 GHz接收机的最后一级下混频。这个混频器使用交流耦合复用电流跨导级。它在低电源电压下性能良好，并且对工艺和温度变化不敏感。这个混频器工作的射频频率范围为10.25–13.75 GHz，本振频率为12 GHz，下混频后的中频频率为直流电平至1.75 GHz。使用65 nm低功耗CMOS工艺流片，整个混频器的面积仅为0.0179 mm2。在1.2 V工作电压、中频10 MHz条件下，测量得到最大电压转换增益为9.8 dB，双边带噪声系数为11.6 dB，输入1 dB压缩点为?13 dBm。这个混频器在1.2 V供电电压下的静态电流为5 mA，整体功耗仅6 mW。

关键词： 折叠混频器,  电流复用,  低功耗,  无电感设计,  直接下变频 
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