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Front. Inform. Technol. Electron. Eng.  2014, Vol. 15 Issue (12): 1200-1210    DOI: 10.1631/jzus.C1400091
    
A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers
Ting Guo, Zhi-qun Li, Qin Li, Zhi-gong Wang
School of Integrated Circuits, Southeast University, Nanjing 210096, China; Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
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Abstract  A 37 GHz wide-band programmable divide-by-N frequency divider (FD) composed of a divide-by-2 divider (acting as the first stage) and a divider with a division ratio range of 273–330 (acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider (with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic (DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as −20 dBm at 32 GHz and the phase noise at 37 GHz is less than −130 dBc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 mW at a supply voltage of 1.2 V and occupies an area of only 730 μm ×475 μm.

Key words： Wide-band      Divide-by-N      Frequency divider      Dynamic current-mode logic (DCML)      Pulse and swallow counters      CMOS     
Received: 14 March 2014      Published: 05 December 2014
CLC:  TN43  
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Ting Guo, Zhi-qun Li, Qin Li, Zhi-gong Wang. A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers. Front. Inform. Technol. Electron. Eng., 2014, 15(12): 1200-1210.

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http://www.zjujournals.com/xueshu/fitee/10.1631/jzus.C1400091     OR     http://www.zjujournals.com/xueshu/fitee/Y2014/V15/I12/1200


应用于硅基毫米波锁相环频率综合器的37GHz宽带可编程模分频器

基于硅基毫米波锁相环设计需求，设计模数连续可变的可编程毫米波分频器。本文的毫米波宽带可编程模分频器采用改进的动态电流模式逻辑结构，包括第一级二分频器和基于吞咽脉冲计数器结构的第二级可编程分频器。实现了毫米波段分频器分频比的连续可调，同时保证了分频器的宽带特性、且功耗较低，该设计适用于毫米波锁相环频率综合器。首先，设计分析毫米波分频器的设计瓶颈，即第一级二分频器。该二分频器处于锁相环环路的最高工作频率处，设计最为复杂。本设计采用改进的动态电流模式逻辑结构，实现了2-40 GHz宽带二分频器（图4）。接着，介绍第二级可编程分频器设计中的核心模块8/9双模分频器（图5、6）。然后，介绍可编程分频器实现分频比连续可调的计数器部分，即吞咽脉冲计数器设计。最后，给出第一级二分频器和整个毫米波宽带可编程模分频器的测试验证曲线。实现基于吞咽计数器的毫米波可编程分频器设计，从而实现毫米波分频器的分频比连续可调和毫米波锁相环频率的高精度调节。测试结果表明本文设计的第一级二分频器能够更好地应用于低功耗宽带可调（表1）的毫米波锁相环。

关键词： 宽带,  模,  分频器,  动态电流模式逻辑,  吞咽脉冲计数器,  CMOS 
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