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Front. Inform. Technol. Electron. Eng.  2014, Vol. 15 Issue (11): 1009-1020    DOI: 10.1631/jzus.C1400055
    
Performance-driven assignment and mapping for reliable networks-on-chips
Qian-qi Le, Guo-wu Yang, William N. N. Hung, Xiao-yu Song, Fu-you Fan
School of Computer Science and Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China; Department of Information and Computing Science, Chengdu University of Technology, Chengdu 610059, China; Synopsys Inc., Mountain View, CA 94040, USA; Department of Electronic and Computer Engineering, Portland State University, Portland, OR 97207-0751, USA
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Abstract  Network-on-chip (NoC) communication architectures present promising solutions for scalable communication requests in large system-on-chip (SoC) designs. Intellectual property (IP) core assignment and mapping are two key steps in NoC design, significantly affecting the quality of NoC systems. Both are NP-hard problems, so it is necessary to apply intelligent algorithms. In this paper, we propose improved intelligent algorithms for NoC assignment and mapping to overcome the drawbacks of traditional intelligent algorithms. The aim of our proposed algorithms is to minimize power consumption, time, area, and load balance. This work involves multiple conflicting objectives, so we combine multiple objective optimization with intelligent algorithms. In addition, we design a fault-tolerant routing algorithm and take account of reliability using comprehensive performance indices. The proposed algorithms were implemented on embedded system synthesis benchmarks suite (E3S). Experimental results show the improved algorithms achieve good performance in NoC designs, with high reliability.

Key wordsNetwork-on-chip (NoC)      Mapping      Assignment      Figs. 1-12

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Received: 19 February 2014      Published: 07 November 2014
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Qian-qi Le
Guo-wu Yang
William N. N. Hung
Xiao-yu Song
Fu-you Fan
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Qian-qi Le, Guo-wu Yang, William N. N. Hung, Xiao-yu Song, Fu-you Fan. Performance-driven assignment and mapping for reliable networks-on-chips. Front. Inform. Technol. Electron. Eng., 2014, 15(11): 1009-1020.

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http://www.zjujournals.com/xueshu/fitee/10.1631/jzus.C1400055     OR     http://www.zjujournals.com/xueshu/fitee/Y2014/V15/I11/1009


性能驱动的可靠片上网络分配和映射

以提高片上网络性能和可靠性为目标,提出片上网络设计中分配和映射这两个重要步骤的优化算法,提出自适应容错路由算法。根据片上网络分配和映射的需求和约束条件,设计了自适应容错路由算法以提高系统可靠性。分别设计了PSOGA、PSOSA和SS三个多目标优化算法,既能满足片上网络分配和映射的需求,又改善了传统智能算法易陷入局部最优的缺点,获得了更多高性能分配和映射方案。首先,根据片上网络分配和映射的需求,分别提出了性能和可靠性的多目标评价模型。接着,设计了自适应的容错路由算法兼顾了系统可靠性和性能。然后,根据片上网络分配和映射的特征,设计了PSOGA和PSOSA算法,融合粒子群、遗传算法和模拟退火算法等传统智能算法的优点,设计了多目标SS算法,实现了基于小种群的多目标优化。最后,将提出的算法用于E3S的典型测试用例,并且通过NIRGAM进行仿真。实验结果显示,本文算法获得的分配和映射方案在质量和数量上均优于传统智能算法。

关键词: 片上网络,  映射,  分配,  可靠性 
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