Accurate mass segmentation on mammograms is a critical step in computer-aided diagnosis (CAD) systems. It is also a challenging task since some of the mass lesions are embedded in normal tissues and possess poor contrast or ambiguous margins. Besides, the shapes and densities of masses in mammograms are various. In this paper, a hybrid method combining a random walks algorithm and Chan-Vese (CV) active contour is proposed for automatic mass segmentation on mammograms. The data set used in this study consists of 1095 mass regions of interest (ROIs). First, the original ROI is preprocessed to suppress noise and surrounding tissues. Based on the preprocessed ROI, a set of seed points is generated for initial random walks segmentation. Afterward, an initial contour of mass and two probability matrices are produced by the initial random walks segmentation. These two probability matrices are used to modify the energy function of the CV model for prevention of contour leaking. Lastly, the final segmentation result is derived by the modified CV model, during which the probability matrices are updated by inserting several rounds of random walks. The proposed method is tested and compared with other four methods. The segmentation results are evaluated based on four evaluation metrics. Experimental results indicate that the proposed method produces more accurate mass segmentation results than the other four methods.

Data sparseness, the evident characteristic of short text, has always been regarded as the main cause of the low accuracy in the classification of short texts using statistical methods. Intensive research has been conducted in this area during the past decade. However, most researchers failed to notice that ignoring the semantic importance of certain feature terms might also contribute to low classification accuracy. In this paper we present a new method to tackle the problem by building a strong feature thesaurus (SFT) based on latent Dirichlet allocation (LDA) and information gain (IG) models. By giving larger weights to feature terms in SFT, the classification accuracy can be improved. Specifically, our method appeared to be more effective with more detailed classification. Experiments in two short text datasets demonstrate that our approach achieved improvement compared with the state-of-the-art methods including support vector machine (SVM) and Na?ve Bayes Multinomial.

It is a well-established fact that wireless sensor networks (WSNs) are very power constraint networks, but besides this, they are inherently more fault-prone than any other type of wireless network and their protocol design is very application specific. Major reasons for the faults are the unpredictable wireless communication channel, battery depletion, as well as fragility and mobility of the nodes. Furthermore, as traditional protocol design methods have proved inadequate, the cross-layer design (CLD) approach, which allows for interactions between different layers, providing more flexible and energy-efficient functionality, has emerged as a viable solution for WSNs. In this study we define a fault tolerance management module suitable to the requirements, limitations, and specifics of WSNs, encompassing methods for fault detection, fault prevention, fault management, and recovery. The suggested solution is in line with the CLD approach, which is an important factor in increasing the network performance. Through simulations the functionality of the network is evaluated, based on packet loss, delay, and energy consumption, and is compared with a similar solution not including fault management. The results achieved support the idea that the introduction of a unified approach to fault management improves the network performance as a whole.

Tracking persons in dangerous situations as well as monitoring their physical condition, is often crucial for their safety. The systems commonly used for this purpose do not include individual monitoring or are too expensive and intrusive to be deployed in common situations. In this project, a mobile system based on energy-efficient wireless sensor networks (WSNs) and active radio frequency identification (RFID) has been developed to achieve ubiquitous positioning and monitoring of people in hazardous situations. The system designed can identify each individual, locate him/her, send data regarding their physical situation, and ascertain whether they are located in a confined space. A new algorithm called time division double beacon scheduling (TDDBS) has been implemented to increase operation time and data transmission rate of the nodes in the system. The results show that the use of this system allows us to find the location and state of a person, as well as to provide an analysis of the potential risks at each moment, in real time and in an energy-efficient way. In an emergency, the system also allows for quicker intervention, as it not only provides the location and causes of the event, but also informs about the physical condition of the individual at that moment.

Echo state network (ESN), which efficiently models nonlinear dynamic systems, has been proposed as a special form of recurrent neural network. However, most of the proposed ESNs consist of complex reservoir structures, leading to excessive computational cost. Recently, minimum complexity ESNs were proposed and proved to exhibit high performance and low computational cost. In this paper, we propose a simple deterministic ESN with a loop reservoir, i.e., an ESN with an adjacent-feedback loop reservoir. The novel reservoir is constructed by introducing regular adjacent feedback based on the simplest loop reservoir. Only a single free parameter is tuned, which considerably simplifies the ESN construction. The combination of a simplified reservoir and fewer free parameters provides superior prediction performance. In the benchmark datasets and real-world tasks, our scheme obtains higher prediction accuracy with relatively low complexity, compared to the classic ESN and the minimum complexity ESN. Furthermore, we prove that all the linear ESNs with the simplest loop reservoir possess the same memory capacity, arbitrarily converging to the optimal value.

For accurate prediction of via yield, via chains are usually fabricated on test chips to investigate issues about vias. To minimize the randomness of experiments and make the testing results more convincing, the confidence level and estimation precision of the via failure rate are investigated in this paper. Based on the Poisson yield model, the method of determining an adequate number of total vias is obtained using the law of large numbers and the de Moivre-Laplace theorem. Moreover, for a specific confidence level and estimation precision, the method of determining a suitable via chain length is proposed. For area minimization, an optimal combination of total vias and via chain length is further determined. Monte Carlo simulation results show that the method is in good accordance with theoretical analyses. Results of via failure rates measured on test chips also reveal that via chains designed using the proposed method has a better performance. In addition, the proposed methodology can be extended to investigate statistical significance for other failure modes.

The floating point number is the most commonly used real number representation for digital computations due to its high precision characteristics. It is used on computers and on single chip applications such as DSP chips. Double precision (64-bit) representations allow for a wider range of real numbers to be denoted. However, single precision (32-bit) operations are more efficient. Recently, there has been an increasing interest in mixed precision computations which take advantage of single precision efficiency on 64-bit numbers. This calls for the ability to interchange between the two formats. In this paper, an algorithm that converts floating point numbers from 64- to 32-bit representations is presented. The algorithm was implemented as a Verilog code and tested on field programmable gate array (FPGA) using the Quartus II DE2 board and Agilent 16821A portable logic analyzer. Results indicate that the algorithm can perform the conversion reliably and accurately within a constant execution time of 25 ns with a 20 MHz clock frequency regardless of the number being converted.