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Front. Inform. Technol. Electron. Eng.  2011, Vol. 12 Issue (7): 604-607    DOI: 10.1631/jzus.C1000372
    
Design of a novel low power 8-transistor 1-bit full adder cell
Yi Wei, Ji-zhong Shen*
Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
Design of a novel low power 8-transistor 1-bit full adder cell
Yi Wei, Ji-zhong Shen*
Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
 全文: PDF(124 KB)  
摘要： An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper we propose a novel 1-bit full adder cell which uses only eight transistors. In this design, three multiplexers and one inverter are applied to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay, and power-delay produced using the new design are analyzed and compared with those of other designs using HSPICE simulations. The results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) value. The low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.
关键词： Full adder design;  Low power;  CMOS circuit;  Very large-scale integration (VLSI)    
Abstract: An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper we propose a novel 1-bit full adder cell which uses only eight transistors. In this design, three multiplexers and one inverter are applied to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay, and power-delay produced using the new design are analyzed and compared with those of other designs using HSPICE simulations. The results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) value. The low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.
Key words: Full adder design    Low power    CMOS circuit    Very large-scale integration (VLSI)
收稿日期: 2010-10-22 出版日期: 2011-07-04
CLC:  TN432  
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引用本文:

Yi Wei, Ji-zhong Shen. Design of a novel low power 8-transistor 1-bit full adder cell. Front. Inform. Technol. Electron. Eng., 2011, 12(7): 604-607.

链接本文:

http://www.zjujournals.com/xueshu/fitee/CN/10.1631/jzus.C1000372    或    http://www.zjujournals.com/xueshu/fitee/CN/Y2011/V12/I7/604

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