电子科学 |
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基于library-free映射的电路面积快速优化算法 |
喻奇, 王伦耀, 夏银水 |
宁波大学 信息科学与工程学院, 浙江 宁波 315211 |
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A fast area optimization method using library-free mapping |
YU Qi, WANG Lunyao, XIA Yinshui |
School of Information Science and Engineering, Ningbo University, Ningbo 315211, Zhejiang Province, China |
[1] MINKOVICH K. Logic Synthesis for Nanometer IC Technologies[D]. Los Angeles:University of California, 2010:201-208.
[2] XUE J Y, AL-KHALILI D, ROZON C N. Technology mapping in library-free logic synthesis[J]. VLSI Circuits and Systems Ⅱ, 2005, 5837:919-928.
[3] 岑旭梦,王伦耀,夏银水. 基于逻辑复合门映射的电路面积优化[J]. 宁波大学学报(理工版), 2016, 29(4):38-43. CEN X X, WANG L Y, XIA Y S. Area optimization based on the complex logic gates mapping[J]. Journal of Ningbo University(Natural Science & Engineering), 2016,29(4):38-43.
[4] AMARU L, GAILLARDON P E, DE MICHELI G. MIXSYN:An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits[C]//18th Asia and South Pacific Design Automation Conference. Yokohama:IEEE, 2013:133-138.
[5] MIRYALA S, TENACE V, CALIMERA A, et al. Exploiting the expressive power of graphene reconfigurable ga-tes via post-synthesis optimization[C]//Proceedings of the 25th Edition on Great Lakes Symposium on VLSI. New York:ACM Press, 2015:39-44.
[6] CONCEIÇāAO C, POSSER G, REIS R. Reducing the number of transistors with gate clustering[C]//7th Latin American Symposium on Circuits & Systems. Florianopolis:IEEE, 2016:163-166.
[7] MARQUES F S, ROSA L S, RIBAS R P, et al. DAG based library-free technology mapping[C]//Great Lakes Symposium on VLSI. NewYork:ACM, 2007:293-298.
[8] El-MASRY H, Al-KHALILI D. Cell stack length using anenhanced logical effort model for a library-free paradigm[C]//IEEE International Conference on Electronics,Circuits and Systems. Beirut:IEEE, 2012:703-706.
[9] CORREIA V, REIS A. Advanced technology mapping forstandard cell generators[C]//Symposium on Integrated Circuits and Systems Design. Porto:IEEE, 2004:254-259.
[10] KADIYALA S P, SAMANTA D. On-the-fly mapping for synthesizing dynamic domino circuits[C]//International Conference on VLSI Design. Bangalore:IEEE, 2015:458-463.
[11] PULLERITS M, KABBANI A. Library-free synthesis for area-delay minimization[C]//International Conference on Microelectronics. Sharjah:IEEE, 2010:187-191.
[12] 陈志辉. FPGA工艺映射算法研究[D]. 上海:复旦大学,2011. CHEN Z H. Research on Algorithms for FPGA Technology Mapping[D]. Shanghai:Fudan University, 2011.
[13] PULLERITS M, KABBANI A. Area minimization for library-free synthesis[C]//IEEE North-East Workshop on Circuits and Systems and TAISA Conference. Toulouse:IEEE, 2009:1-4. |
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