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浙江大学学报（理学版）
浙江大学学报（理学版）  2016, Vol. 43 Issue (6): 689-695    DOI: 10.3785/j.issn.1008-9497.2016.06.013
电子科学     
增强工艺偏差容忍度的带隙基准电压源设计
俞淼, 罗小华, 卢宇峰, 李益航
浙江大学 超大规模集成电路研究所, 浙江 杭州 310027
Bandgap voltage reference design with enhanced tolerance of process variations
YU Miao, LUO Xiaohua, LU Yufeng, LI Yihang
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
 全文: PDF(1844 KB)  
摘要： 随着CMOS工艺特征尺寸的减小，带隙基准电压源在制造过程中因器件失配和工艺波动易导致实际输出电压和目标值发生偏离，降低芯片成品率.为此提出将Pelgrom失配模型引入电路设计中，分别从器件参数、电路结构、版图布局三方面对亚微米级的电路进行工艺偏差优化.基于华润上华（CSMC）0.5 μm工艺以及Hspice软件仿真，显示基准源输出电压为1.232 54 V，偏差小于5 mV.流片测试结果表明，应用此设计的三通道LED驱动控制芯片成品率达到96.8%，输出电流达到（18±0.5）mA的芯片占99.6%以上.
关键词： 工艺偏差;  失配;  带隙基准电压;  阈值偏差;  失调;  成品率    
Abstract: As the feature size of CMOS technology is scaled down, devices mismatch and process tolerance will lead to deviation in bandgap reference voltage, which significantly impacts manufacturing cost by decreasing yield. Based on the Pelgrom's mismatch model, this paper proposes a design methodology from three aspects: parameters, schematic and layout. Hspice simulation result shows that the output of the bandgap reference circuit is(1.232 54±0.005)V in CSMC 0.5 μm technology. Applying this design in 3 channels LED driver chips, the test results indicate that the yield reaches 96.8%, while the chips that meet the output current requirements of(18±0.5) mA account for above 99.6%.
Key words: process variations    mismatch    bandgap voltage reference    threshold deviations    offset    yield
收稿日期: 2015-12-04 出版日期: 2017-03-07
CLC:  TN386  
基金资助: 浙江省自然科学基金资助项目(LY15F040001).
通讯作者: 罗小华,ORCID:http://orcid.org/0000-0002-2807-2386,E-mail:luoxh@vlsi.zju.edu.cn     E-mail: luoxh@vlsi.zju.edu.cn
作者简介: 俞淼(1991-),ORCID:http://orcid.org/0000-0002-8110-1334,女,硕士,主要从事超大规模集成电路研究,E-mail:yumiao@zju.edu.cn.
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引用本文:

俞淼, 罗小华, 卢宇峰, 李益航. 增强工艺偏差容忍度的带隙基准电压源设计[J]. 浙江大学学报（理学版）, 2016, 43(6): 689-695.

YU Miao, LUO Xiaohua, LU Yufeng, LI Yihang. Bandgap voltage reference design with enhanced tolerance of process variations. Journal of ZheJIang University(Science Edition), 2016, 43(6): 689-695.

链接本文:

https://www.zjujournals.com/sci/CN/10.3785/j.issn.1008-9497.2016.06.013    或    https://www.zjujournals.com/sci/CN/Y2016/V43/I6/689

[1] IVANOV V, BREDERLOW R, GERBER J. An ultra low power bandgap operational at supply from 0.75 V[J]. Solid-State Circuits, 2012,47(7):1515-1523.
[2] BANERJEE A, CHATTERJEE A. Signature driven hierarchical post-manufacture tuning of RF systems for performance and power[J]. IEEE Transactions on Very Large Scale Integration Systems, 2015,23(2):342-355.
[3] RADFAR M, SINGH J. A yield improvement technique in severe process, voltage, and temperature variations and extreme voltage scaling[J]. Microelectronics Reliability, 2014, 54(12):2813-2823.
[4] 刘博,张雷鸣,王金婵.基于D/A转换器的工艺波动表征方法的研究[J].微电子学与计算机,2015,3(3):117-121. LIU Bo, ZHANG Leiming, WANG Jinchan. Research on characterization methodology for process variation with D/A converters[J]. Microelectronics & Computer,2015,3(3):117-121.
[5] 吕伟锋,孙玲玲.一个简单的65 nm MOSFET失配模型[J].计算机辅助设计与图形学学报,2011,23(7):1280-1284. LYU Weifeng, SUN Lingling. A simplified 65 nm MOSFET mismatch model[J]. Journal of Computer-Aided Design & Computer Graphics, 2011,23(7):1280-1284.
[6] LAKSHMIKUMAR K R, HADAWAY R A, COPELAND M A. Characterization and modeling of mismatch in MOS transistors for precision analog design[J]. IEEE Journal of Solid-State Circuits, 1986,21(6):1057-1066.
[7] PELGROM M. Matching properties of MOS transistors[J]. IEEE Journal of Solid-State Circuits,1989,305(3):1433-1439.
[8] PAPATHANASIOU K. A designer's approach to device mismatch:Theory, modeling, simulation techniques, scripting, applications and examples[J]. Analog Integrated Circuits & Signal Processing, 2006,48(2):95-106.
[9] WIDLAR R J. New developments in IC voltage regulators[J]. IEEE Journal of Solid-state Circuits,1971,6(1):2-7.
[10] 代国定,徐洋,李卫敏,等.高性能分段温度曲率补偿基准电压源设计[J].浙江大学学报:工学版,2010(11):2142-2147. DAI Guoding, XU Yang, LI Weimin, et al. Design of high performance bandgap reference based on piecewise temperature curvature compensated technology[J]. Journal of Zhejiang University:Engineering Science,2010(11):2142-2147.
[11] 汤华莲,庄奕琪,张丽,等.一种可校准的低温漂基准电流源[J].西安电子科技大学学报:自然科学版,2013,40(4):130-136. TANG Hualian, ZHUANG Yiqi, ZHANG Li, et al. Design of a trimmed current reference with a low temperature drift[J]. Journal of Xidian University:Natural Sciences,2013,40(4):130-136.
[12] 张献中,张涛.一种三阶曲率补偿带隙基准电压源的设计[J].武汉科技大学学报,2015(1):67-71. ZHANG Xianzhong, ZHANG Tao. A bandgap voltage reference with third-order curvature compensation[J]. Journal of Wuhan University of Science and Technology,2015(1):67-71.
[13] KINGET P R. Device mismatch and tradeoffs in the design of analog circuits[J]. IEEE Journal of Solid-State Circuits, 2005,40(6):1212-1224.
[14] GUPTA V, RINCÓN-MORA G. Predicting and designing for the impact of process variations and mismatch on the trim range and yield of bandgap references[C]//Quality of Electronic Design, ISQED 2005. Sixth International Symposium on IEEE. San Jose:IEEE,2005:503-508.
[15] LYU Weifeng, SUN Lingling. Modeling of current mismatch induced by random dopant fluctuation in nano-MOSFETs[J]. Chinese Journal of Semiconductors,2011(8):46-50.
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