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Chinese Journal of Engineering Design  2013, Vol. 20 Issue (1): 80-84    DOI:
    
Research and design of ethernet interface in embedded equipment
 CHEN  Jian-Ming, MENG  Han
Institute of Electric Power, North China University of Water Resources and Electric Power, Zhengzhou 450011, China
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Abstract  In order to solve the question of slow speed Ethernet transmission in traditional embedded equipment, an implement method based on FPGA and W5100 was designed. The NiosⅡprocessor which was created by SOPC technology was used to control hardware TCP/IP protocol W5100 to realize Ethernet transmission, and C2H was used to do hardware accelerator for crucial C code. This system transmits data reliably and has much faster transmission speed than traditional methods, realizing high-speed Ethernet transmission.

Key wordsSOPC      NiosⅡ      W5100      hardware acceleration     
Published: 28 February 2013
Cite this article:

CHEN Jian-Ming, MENG Han. Research and design of ethernet interface in embedded equipment. Chinese Journal of Engineering Design, 2013, 20(1): 80-84.

URL:

https://www.zjujournals.com/gcsjxb/     OR     https://www.zjujournals.com/gcsjxb/Y2013/V20/I1/80


嵌入式设备以太网接口的设计研究

针对传统嵌入式设备中以太网传输速度慢的问题,研制了一种基于FPGA和W5100的高速以太网实现方案.采用SOPC技术配置NiosⅡ处理器,控制硬件TCP/IP协议栈W5100芯片实现设备的以太网传输,并利用C2H对W5100中的关键C代码进行硬件提速.该系统传输数据可靠,传输速度较传统实现方法有显著提高,实现了系统的高速网络传输.

关键词: SOPC,  NiosⅡ,  W5100,  硬件提速 
[1] WANG Ting-Ling, LIANG Yan, CHEN Jian-Ming. Design of networked access management system based on W5100[J]. Chinese Journal of Engineering Design, 2012, 19(5): 412-416.