| Electrical & Electronic Engineering |
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| Design of adiabatic two’s complement multiplier-accumulator based on CTGAL |
| Peng-jun WANG, Jian XU, Shi-yan YING |
| Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China; College of Information Engineering, Zhejiang University of Technology, Hangzhou 310014, China |
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Abstract We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic (CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two’s complement multiplier-accumulator (MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor (CMOS) logic.
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Received: 05 January 2008
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