| Electrical & Electronic Engineering |
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| Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder |
| Wan-yi LI, Lu YU |
| Institute of Information and Communication Engineering, Zhejiang University, Hangzhou 310027, China |
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Abstract In this paper, we propose an effective VLSI architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV (1 920×1 088) 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints.
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Received: 18 February 2008
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