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ZJUS-A
Journal of Zhejiang University-SCIENCE A (Applied Physics & Engineering)  2004, Vol. 5 Issue ( 9): 12-    DOI: 10.1631/jzus.2004.1102
    
A front-end automation tool supporting design, verification and reuse of SOC
YAN Xiao-lang, YU Long-li, WANG Jie-bing
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; C-Sky Microsystems, Hangzhou 310032, China
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Abstract  This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.

Key words： System-On-Chip      Verilog      HDL      Verification      Reuse     
Received: 18 March 2003     
CLC:  TN402  
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YAN Xiao-lang
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YAN Xiao-lang, YU Long-li, WANG Jie-bing. A front-end automation tool supporting design, verification and reuse of SOC. Journal of Zhejiang University-SCIENCE A (Applied Physics & Engineering), 2004, 5( 9): 12-.

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http://www.zjujournals.com/xueshu/zjus-a/10.1631/jzus.2004.1102     OR     http://www.zjujournals.com/xueshu/zjus-a/Y2004/V5/I 9/12

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