| Information & Computer Science |
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| Physical design method of MPSoC |
| LIU Peng, XIA Bing-jie, TENG Zhao-wei |
| Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China |
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Abstract Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel diagonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network containing hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.
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Received: 21 September 2006
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