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ZJUS-A
Journal of Zhejiang University-SCIENCE A (Applied Physics & Engineering)  2003, Vol. 4 Issue (3): 281-286    DOI: 10.1631/jzus.2003.0281
Electrical Engineering     
Noise and linearity optimization methods for a 1.9GHz low noise amplifier
GUO Wei, HUANG Da-quan
Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
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Abstract  Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade-offs. The 1.9GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.

Key words： RFIC      CMOS LNA      noise      IP3      linearity     
Received: 03 May 2002     
CLC:  TN722.3  
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GUO Wei
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GUO Wei, HUANG Da-quan. Noise and linearity optimization methods for a 1.9GHz low noise amplifier. Journal of Zhejiang University-SCIENCE A (Applied Physics & Engineering), 2003, 4(3): 281-286.

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http://www.zjujournals.com/xueshu/zjus-a/10.1631/jzus.2003.0281     OR     http://www.zjujournals.com/xueshu/zjus-a/Y2003/V4/I3/281

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