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Front. Inform. Technol. Electron. Eng.  2011, Vol. 12 Issue (1): 76-82    DOI: 10.1631/jzus.C1000234
    
A pipelined architecture for normal I/O order FFT
Xue Liu, Feng Yu*, Ze-ke Wang
Department of Instrument Engineering, Zhejiang University, Hangzhou 310027, China
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Abstract  We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

Key wordsFast Fourier transform (FFT)      Single-path delay commutator (SDC)      Pipelined FFT      Bit reverser     
Received: 02 July 2010      Published: 10 January 2010
CLC:  TN91  
Cite this article:

Xue Liu, Feng Yu, Ze-ke Wang. A pipelined architecture for normal I/O order FFT. Front. Inform. Technol. Electron. Eng., 2011, 12(1): 76-82.

URL:

http://www.zjujournals.com/xueshu/fitee/10.1631/jzus.C1000234     OR     http://www.zjujournals.com/xueshu/fitee/Y2011/V12/I1/76


A pipelined architecture for normal I/O order FFT

We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

关键词: Fast Fourier transform (FFT),  Single-path delay commutator (SDC),  Pipelined FFT,  Bit reverser 
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