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Front. Inform. Technol. Electron. Eng.  2014, Vol. 15 Issue (2): 153-160    DOI: 10.1631/jzus.C1300249
    
High-speed, fixed-latency serial links with Xilinx FPGAs
Xue Liu, Qing-xu Deng, Bo-ning Hou, Ze-ke Wang
Institute of Cyber-Physical System Engineering, Northeastern University, Shenyang 110004, China; Institute of Digital Technology and Instruments, Zhejiang University, Hangzhou 310027, China
High-speed, fixed-latency serial links with Xilinx FPGAs
Xue Liu, Qing-xu Deng, Bo-ning Hou, Ze-ke Wang
Institute of Cyber-Physical System Engineering, Northeastern University, Shenyang 110004, China; Institute of Digital Technology and Instruments, Zhejiang University, Hangzhou 310027, China
 全文: PDF 
摘要： High-speed, fixed-latency serial links find application in distributed data acquisition and control systems, such as the timing trigger and control (TTC) system for high energy physics experiments. However, most high-speed serial transceivers do not keep the same chip latency after each power-up or reset, as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this paper, we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays (FPGAs). First, we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver. Second, we use the internal alignment circuit of the transceiver and a digital clock manager (DCM)/phase-locked loop (PLL) based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver. The test results of the link latency are shown. Compared with existing solutions, our design not only implements fixed chip latency, but also reduces the average system lock time.
关键词： Data acquisition circuit;  Fixed-latency;  Field programmable gate array (FPGA);  Serial link;  Trigger system    
Abstract: High-speed, fixed-latency serial links find application in distributed data acquisition and control systems, such as the timing trigger and control (TTC) system for high energy physics experiments. However, most high-speed serial transceivers do not keep the same chip latency after each power-up or reset, as there is no deterministic phase relationship between the transmitted and received clocks after each power-up. In this paper, we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays (FPGAs). First, we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver. Second, we use the internal alignment circuit of the transceiver and a digital clock manager (DCM)/phase-locked loop (PLL) based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver. The test results of the link latency are shown. Compared with existing solutions, our design not only implements fixed chip latency, but also reduces the average system lock time.
Key words: Data acquisition circuit    Fixed-latency    Field programmable gate array (FPGA)    Serial link    Trigger system
收稿日期: 2013-09-11 出版日期: 2014-01-29
CLC:  TN79  
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Xue Liu
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引用本文:

Xue Liu, Qing-xu Deng, Bo-ning Hou, Ze-ke Wang. High-speed, fixed-latency serial links with Xilinx FPGAs. Front. Inform. Technol. Electron. Eng., 2014, 15(2): 153-160.

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http://www.zjujournals.com/xueshu/fitee/CN/10.1631/jzus.C1300249    或    http://www.zjujournals.com/xueshu/fitee/CN/Y2014/V15/I2/153

[1] Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang. An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays[J]. Front. Inform. Technol. Electron. Eng., 2011, 12(4): 323-329.