Please wait a minute...
FITEE
Front. Inform. Technol. Electron. Eng.  2011, Vol. 12 Issue (1): 76-82    DOI: 10.1631/jzus.C1000234
    
A pipelined architecture for normal I/O order FFT
Xue Liu, Feng Yu*, Ze-ke Wang
Department of Instrument Engineering, Zhejiang University, Hangzhou 310027, China
A pipelined architecture for normal I/O order FFT
Xue Liu, Feng Yu*, Ze-ke Wang
Department of Instrument Engineering, Zhejiang University, Hangzhou 310027, China
 全文: PDF(165 KB)  
摘要： We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
关键词： Fast Fourier transform (FFT);  Single-path delay commutator (SDC);  Pipelined FFT;  Bit reverser    
Abstract: We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
Key words: Fast Fourier transform (FFT)    Single-path delay commutator (SDC)    Pipelined FFT    Bit reverser
收稿日期: 2010-07-02 出版日期: 2010-01-10
CLC:  TN91  
通讯作者: Feng Yu     E-mail: osfengyu@zju.edu.cn
服务　　
把本文推荐给朋友
加入引用管理器
E-mail Alert
RSS
作者相关文章　　
Xue Liu
Feng Yu
Ze-ke Wang

引用本文:

Xue Liu, Feng Yu, Ze-ke Wang. A pipelined architecture for normal I/O order FFT. Front. Inform. Technol. Electron. Eng., 2011, 12(1): 76-82.

链接本文:

http://www.zjujournals.com/xueshu/fitee/CN/10.1631/jzus.C1000234    或    http://www.zjujournals.com/xueshu/fitee/CN/Y2011/V12/I1/76

[1] Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang. An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays[J]. Front. Inform. Technol. Electron. Eng., 2011, 12(4): 323-329.
[2] Dan Wu, Xue-cheng Zou, Kui Dai, Jin-li Rao, Pan Chen, Zhao-xia Zheng. Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture[J]. Front. Inform. Technol. Electron. Eng., 2011, 12(12): 976-989.
[3] Lei Zhang, Peng Liu, Yu-ling Liu, Fei-hong Yu. High quality multi-focus polychromatic composite image fusion algorithm based on filtering in frequency domain and synthesis in space domain[J]. Front. Inform. Technol. Electron. Eng., 2010, 11(5): 365-374.