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Front. Inform. Technol. Electron. Eng.  2011, Vol. 12 Issue (6): 499-506    DOI: 10.1631/jzus.C1000201
    
An efficient hardware design for HDTV H.264/AVC encoder
Liang Wei1,2, Dan-dan Ding1,2, Juan Du1,2, Bin-bin Yu1,2, Lu Yu*,1,2
1 Institute of Information and Communication Engineering, Zhejiang University, Hangzhou 310027, China 2 Zhejiang Provincial Key Laboratory of Information Network Technology, Hangzhou 310027, China
An efficient hardware design for HDTV H.264/AVC encoder
Liang Wei1,2, Dan-dan Ding1,2, Juan Du1,2, Bin-bin Yu1,2, Lu Yu*,1,2
1 Institute of Information and Communication Engineering, Zhejiang University, Hangzhou 310027, China 2 Zhejiang Provincial Key Laboratory of Information Network Technology, Hangzhou 310027, China
 全文: PDF(187 KB)  
摘要： This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile.
关键词： H.264/AVC;  High-definition television (HDTV);  Hardware;  Architecture;  Encoder     
Abstract: This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile.
Key words: H.264/AVC    High-definition television (HDTV)    Hardware    Architecture    Encoder
收稿日期: 2010-06-16 出版日期: 2011-06-07
CLC:  TN919.8  
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Liang Wei
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引用本文:

Liang Wei, Dan-dan Ding, Juan Du, Bin-bin Yu, Lu Yu. An efficient hardware design for HDTV H.264/AVC encoder. Front. Inform. Technol. Electron. Eng., 2011, 12(6): 499-506.

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http://www.zjujournals.com/xueshu/fitee/CN/10.1631/jzus.C1000201    或    http://www.zjujournals.com/xueshu/fitee/CN/Y2011/V12/I6/499

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