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Journal of Zhejiang University-SCIENCE A (Applied Physics & Engineering)  2008, Vol. 9 Issue (12): 1708-1714    DOI: 10.1631/jzus.A0720117
Electrical & Electronic Engineering     
A low-power high-throughput link splitting router for NoCs
Mohsen SANEEI, Ali AFZALI-KUSHA, Zainalabedin NAVABI
Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
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Abstract  In this paper, we propose a technique for lowering the latency of the communication in a NoC (network on chip). The technique, which can support two qualities of service (QoS), i.e., the guaranteed throughput (GT) and best effort (BE), is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the synchronization and reduce the crosstalk, we use the 1-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.

Key wordsLow-power      Latency      Throughput      Network on chip (NoC)      Delay-insensitive      Router     
Received: 12 December 2007     
CLC:  TN402  
Cite this article:

Mohsen SANEEI, Ali AFZALI-KUSHA, Zainalabedin NAVABI. A low-power high-throughput link splitting router for NoCs. Journal of Zhejiang University-SCIENCE A (Applied Physics & Engineering), 2008, 9(12): 1708-1714.

URL:

http://www.zjujournals.com/xueshu/zjus-a/10.1631/jzus.A0720117     OR     http://www.zjujournals.com/xueshu/zjus-a/Y2008/V9/I12/1708

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