Underwater gliders are efficient mobile sensor platforms that can be deployed for months at a time, traveling thousands of kilometers. Here, we describe our development of a coastal 200 m deep underwater glider, which can serve as an ocean observatory platform operating in the East China Sea. Our glider is developed based on dynamic model analysis: steady flight equilibrium analysis gives the varied range of moving mass location for pitch control and the varied vehicle volume for buoyancy control; a stability analysis is made to discuss the relationship between the stability of glider motion and the location of glider wings and rudder by root locus investigation of glider longitudinal- and lateral-directional dynamics, respectively. There is a tradeoff between glider motion stability and control authority according to the specific glider mission requirements. The theoretical analysis provides guidelines for vehicle design, based on which we present the development progress of the Zhejiang University (ZJU) glider. The mechanical, electrical, and software design of the glider is discussed in detail. The performances of glider key functional modules are validated by pressure tests individually; preliminary pool trials of the ZJU glider are also introduced, indicating that our glider functions well in water and can serve as a sensor platform for ocean sampling.

In a self-sensing active magnetic bearing (AMB) system driven by pulse width modulation (PWM) switching power amplifiers, the rotor position information can be extracted from coil current and voltage signals by a specific signal demodulation process. In this study, to reduce the complexity of hardware, the coil voltage signal was not filtered but measured in the form of a duty cycle by the eCAP port of DSP (TMS320F28335). A mathematical model was established to provide the relationship between rotor position, current ripple, and duty cycle. Theoretical analysis of the amplitude-frequency characteristic of the coil current at the switching frequency was presented using Fourier series, Jacobi-Anger identity, and Bessel function. Experimental results showed that the time-varying duty cycle causes infinite side frequencies around the switching frequency. The side frequency interval depends on the varying frequency of the duty cycle. Rotor position can be calculated by measuring the duty cycle and demodulating the coil current ripple. With this self-sensing strategy, the rotor system supported by AMBs can steadily rotate at a speed of 3000 r/min.

Membrane algorithms are a class of distributed and parallel algorithms inspired by the structure and behavior of living cells. Many attractive features of living cells have already been abstracted as operators to improve the performance of algorithms. In this work, inspired by the function of biological neuron cells storing information, we consider a memory mechanism by introducing memory modules into a membrane algorithm. The framework of the algorithm consists of two kinds of modules (computation modules and memory modules), both of which are arranged in a ring neighborhood topology. They can store and process information, and exchange information with each other. We test our method on a knapsack problem to demonstrate its feasibility and effectiveness. During the process of approaching the optimum solution, feasible solutions are evolved by rewriting rules in each module, and the information transfers according to directions defined by communication rules. Simulation results showed that the performance of membrane algorithms with memory cells is superior to that of algorithms without memory cells for solving a knapsack problem. Furthermore, the memory mechanism can prevent premature convergence and increase the possibility of finding a global solution.

We propose the usage of formal languages for expressing instances of NP-complete problems for their application in polynomial transformations. The proposed approach, which consists of using formal language theory for polynomial transformations, is more robust, more practical, and faster to apply to real problems than the theory of polynomial transformations. In this paper we propose a methodology for transforming instances between NP-complete problems, which differs from Garey and Johnson’s. Unlike most transformations which are used for proving that a problem is NP-complete based on the NP-completeness of another problem, the proposed approach is intended for extrapolating some known characteristics, phenomena, or behaviors from a problem A to another problem B. This extrapolation could be useful for predicting the performance of an algorithm for solving B based on its known performance for problem A, or for taking an algorithm that solves A and adapting it to solve B.

Several ensemble-based three-dimensional variational (3D-Var) filters are compared. These schemes replace the static background error covariance of the traditional 3D-Var with the ensemble forecast error covariance, but generate analysis ensemble anomalies (perturbations) in different ways. However, it is demonstrated in this paper that they are all theoretically equivalent to the ensemble transformation Kalman filter (ETKF). Furthermore, a new method named EnPSAS is presented. The analysis shows that EnPSAS has a small condition number and can apply covariance localization more easily than other ensemble-based 3D-Var methods.

This paper deals with an in-line network security processor (NSP) design that implements the Internet Protocol Security (IPSec) protocol processing for the 10 Gbps Ethernet. The 10 Gbps high speed data transfer, the IPSec processing including the crypto-operation, the database query, and IPSec header processing are integrated in the design. The in-line NSP is implemented using 65 nm CMOS technology and the layout area is 2.5 mm×3 mm with 360 million gates. A configurable crossbar data transfer skeleton implementing an iSLIP scheduling algorithm is proposed, which enables simultaneous data transfer between the heterogeneous multiple cores. There are, in addition, a high speed input/output data buffering mechanism and design of high performance hardware structures for modules, wherein the transfer efficiency and the resource utilization are maximized and the IPSec protocol processing achieves 10 Gbps line speed. A high speed and low power hardware look-up method is proposed, which effectively reduces the area and power dissipation. The post simulation results demonstrate that the design gives a peak throughput for the Authentication Header (AH) transport mode of 10.06 Gbps with the average test packet length of 512 bytes under the clock rate of 250 MHz, and power dissipation less than 1 W is obtained. An FPGA prototype is constructed to verify the function of the design. A test bench is being set up for performance and function verification.

A digital controller IC for the flyback converter with primary-side feedback is proposed. The controller is used for adapter charger or LED driver applications. To obtain high accuracy for the primary-side feedback, a digital primary-side sensing technology is adopted, which can auto-track the knee point of the primary auxiliary winding voltage. Furthermore, an internal digital compensator eliminates the need for external loop compensation components while achieving excellent line and load regulation. The controller could output both constant voltage and constant current depending on the load current. Pulse width modulation and pulse frequency modulation are used in constant voltage mode while quasi-resonant control is used in constant current mode. The digital controller is validated by using FPGA.