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Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer |
Di Li*,1, Yin-tang Yang1, Jiang-an Wang1,2, Bing Li1, Qiang Long1,2, Jary Wei2, Nai-di Wang2, Lei Wang2, Qian-kun Liu2, Da-long Zhang2 |
1 School of Microelectronics, Xidian University, Xi'an 710071, China
2 Huaxun Microelectronics Corporation, Xi'an 710075, China
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Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer |
Di Li*,1, Yin-tang Yang1, Jiang-an Wang1,2, Bing Li1, Qiang Long1,2, Jary Wei2, Nai-di Wang2, Lei Wang2, Qian-kun Liu2, Da-long Zhang2 |
1 School of Microelectronics, Xidian University, Xi'an 710071, China
2 Huaxun Microelectronics Corporation, Xi'an 710075, China
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引用本文:
Di Li, Yin-tang Yang, Jiang-an Wang, Bing Li, Qiang Long, Jary Wei, Nai-di Wang, Lei Wang, Qian-kun Liu, Da-long Zhang. Design of a low power GPS receiver in 0.18 μm CMOS technology with a ΣΔ fractional-N synthesizer. Front. Inform. Technol. Electron. Eng., 2010, 11(6): 444-449.
链接本文:
http://www.zjujournals.com/xueshu/fitee/CN/10.1631/jzus.C0910381
或
http://www.zjujournals.com/xueshu/fitee/CN/Y2010/V11/I6/444
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