低抖动快锁定10.9~12.0 GHz电荷泵锁相环

展永政,李仁刚,李拓,邹晓峰,周玉龙,胡庆生,李连鸣

Low-jitter fast-locked 10.9−12.0 GHz charge-pump phase-locked loop

Yongzheng ZHAN,Rengang LI,Tuo LI,Xiaofeng ZOU,Yulong ZHOU,Qingsheng HU,Lianming LI

表 1 65 nm 工艺下的CPPLL性能总结与比较

Tab.1 Summary and comparison of CPPLL performance using 65 nm technology

文献 VCO 锁频范围/GHz RMS /ps 相位噪声/(dB·Hz−1) 参考杂散/dB 功耗/mW 面积/mm2 FoM/dB 本文 LC 10.9~12.0 0.9739 −111.47@10 MHz −25.14 47.3 0.309 −223.5 文献[24] LC 1.25~3.125 2.17 — — 43.6 — −216.8 文献[25] LC 6.3~8.7 1.2 −116.6@1 MHz <−50 50 0.72 −161.4 文献[26] LC 3.6 0.043 −141.1@1 MHz −80.34 7.27 0.497 −258.7 文献[27] Ring 3.2 7.5 −107.9@10 MHz −45.5 2.73 0.047 −218.1 文献[28] Ring 1.25~3.125 1.65 — −47.63 28.8 0.384 −221.1 文献[29] Ring 1.2~2.5 0.25 −124.8@1 MHz −46 8.5 0.0066 −242.7