H.266/VVC二维变换的统一硬件结构

陈俊煜,孙斌,黄晓峰,盛庆华,赖昌材,金心宇

Unified hardware architecture for 2D transform in H.266/VVC

Jun-yu CHEN,Bin SUN,Xiao-feng HUANG,Qing-hua SHENG,Chang-cai LAI,Xin-yu JIN

表 1 基于ASIC实现的二维变换硬件设计对比

Tab.1 Comparison of 2D transform hardware designs based on ASIC

方法 标准 工艺 F/MHz H/(像素·周期−1) NGC/103 P/mW N 变换类型 DCT-II DST-VII DCT-VIII 文献[10] VVC 65 nm 250 32 496.4 62.6 4~32 × √ √ 文献[13] VVC 28 nm 600 1 89.1 — 4~64 √ √ √ 文献[14] VVC 90 nm 160 8 416.0 — 4~32 √ √ √ 文献[17] HEVC 90 nm 187 32 347.0 67.6 4~32 √ × × 文献[21] HEVC 90 nm 300 8,8,4,2 166.0 23.2 4~32 √ × × 本研究 VVC 28 nm 724 32 1 121.5 48.2 4~64 √ √ √