多芯片小数分频锁相环输出信号相位同步设计
Design of multi chip fractional frequency phase locked loop output signal phase synchronization
多芯片小数分频锁相环输出信号相位同步设计 |
| 徐砚天,黄晓敏,李浩明,王志宇,郁发新 |
|
Design of multi chip fractional frequency phase locked loop output signal phase synchronization |
| Yan-tian XU,Xiao-min HUANG,Hao-ming LI,Zhi-yu WANG,Fa-xin YU |
| 图 9 2个PLL输出信号之间相位差随时间变化曲线 |
| Fig.9 Curve of phase difference with time between two PLL output signals |
|
|