多芯片小数分频锁相环输出信号相位同步设计 |
徐砚天,黄晓敏,李浩明,王志宇,郁发新 |
Design of multi chip fractional frequency phase locked loop output signal phase synchronization |
Yan-tian XU,Xiao-min HUANG,Hao-ming LI,Zhi-yu WANG,Fa-xin YU |
图 8 相位同步后2个PLL输出信号 |
Fig.8 Two PLL output signals after phase synchronization |
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